XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 253

• Manufacturer Part Number: XC68HC12A0CPV8
• Description: IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
• Manufacturer: Freescale Semiconductor

Specifications of XC68HC12A0CPV8

• Controller Family/series: 68HC12
• No. Of I/o's: 68
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Core Size: 16 Bit
• Program Memory Size: 60KB
• Peripherals: ADC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
PACMX — 8-Bit Pulse Accumulators Maximum Count
BUFEN — IC Buffer Enable
LATQ — Input Control Latch or Queue Mode Enable
the main timer contents. At the next event the TCn data is transferred
to the TCnH register, The TCn is updated and the CnF interrupt flag
is set. See
In all other input capture cases the interrupt flag is set by a valid
external event on PTn.
The BUFEN control bit should be set in order to enable the IC and
pulse accumulators holding registers. Otherwise LATQ latching
modes are disabled.
Write one into ICLAT bit in MCCTL ($A6), when LATQ and BUFEN
are set will produce latching of input capture and pulse accumulators
registers into their holding registers.
0 = The timer flags C3F–C0F in TFLG1 ($8E) are set when a valid
1 = If in queue mode (BUFEN=1 and LATQ=0), the timer flags
0 = Normal operation. When the 8-bit pulse accumulator has
1 = When the 8-bit pulse accumulator has reached the value $FF,
0 = Input Capture and pulse accumulator holding registers are
1 = Input Capture and pulse accumulator holding registers are
input capture transition on the corresponding port pin occurs.
C3F–C0F in TFLG1 ($8E) are set only when a latch on the
corresponding holding register occurs.
If the queue mode is not engaged, the timer flags C3F–C0F are
set the same way as for TFMOD=0.
reached the value $FF, with the next active edge, it will be
incremented to $00.
it will not be incremented further. The value $FF indicates a
count of 255 or more.
disabled.
enabled. The latching mode is defined by LATQ control bit.
Write one into ICLAT bit in MCCTL ($A6), when LATQ is set
will produce latching of input capture and pulse accumulators
registers into their holding registers.
Enhanced Capture Timer
Figure
14-6.
Enhanced Capture Timer
Timer Registers
Technical Data
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