XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 346

• Manufacturer Part Number: XC68HC12A0CPV8
• Description: IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
• Manufacturer: Freescale Semiconductor

Specifications of XC68HC12A0CPV8

• Controller Family/series: 68HC12
• No. Of I/o's: 68
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Core Size: 16 Bit
• Program Memory Size: 60KB
• Peripherals: ADC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MSCAN Controller
17.13.15 msCAN12 Port CAN Control Register (PCTLCAN)
Technical Data
346
PCTLCAN
$013D
RESET
R
W
NOTE:
Bit 7
0
0
AM7 – AM0 — Acceptance Mask Bits
The CIDMR0–7 registers can only be written if the SFTRES bit in
CMCR0 is set.
The following bits control pins 7 through 2 of Port CAN. Pins 1 and 0 are
reserved for the RxCan (input only) and TxCan (output only) pins.
PUPCAN — Pull-Up Enable Port CAN
In 80QFP all PortCAN[2:7] pins should either be defined as outputs or
have their pull-ups enabled.
RDPCAN — Reduced Drive Port CAN
If a particular bit in this register is cleared this indicates that the
corresponding bit in the identifier acceptance register must be the same
as its identifier bit, before a match is detected. The messageis accepted
if all such bits match. If a bit is set, it indicates that the state of the
corresponding bit in the identifier acceptance register does not affect
whether or not the message is accepted.
Bit description:
6
0
0
0 = Match corresponding acceptance code register and identifier
1 = Ignore corresponding acceptance code register bit.
0 = Pull mode disabled for Port CAN.
1 = Pull mode enabled for Port CAN.
0 = Reduced drive disabled for Port CAN.
1 = Reduced drive enabled for Port CAN.
bits.
5
0
0
MSCAN Controller
4
0
0
3
0
0
2
0
0
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
PUPCAN
1
0
RDPCAN
Bit 0
0