XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 400
XC68HC12A0CPV8
Manufacturer Part Number
XC68HC12A0CPV8
Description
IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
Manufacturer
Freescale Semiconductor
Datasheet
1.MC912D60ACFUE8.pdf
(460 pages)
Specifications of XC68HC12A0CPV8
Controller Family/series
68HC12
No. Of I/o's
68
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
1
Core Size
16 Bit
Program Memory Size
60KB
Peripherals
ADC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Technical Data
400
BKMBL — Breakpoint Mask Low
BK1RWE — R/W Compare Enable
BK1RW — R/W Compare Value
BK0RWE — R/W Compare Enable
BK0RW — R/W Compare Value
Disables the matching of the low byte of data when in full breakpoint
mode. Used in conjunction with the BKDBE bit (which should be set)
Enables the comparison of the R/W signal to further specify what
causes a match. This bit is NOT useful in program breakpoints or in
full breakpoint mode. This bit is used in conjunction with a second
address in dual address mode when BKDBE=1.
When BK1RWE = 1, this bit determines the type of bus cycle to
match.
Enables the comparison of the R/W signal to further specify what
causes a match. This bit is not useful in program breakpoints.
When BK0RWE = 1, this bit determines the type of bus cycle to match
on.
0 = Low byte of data bus (bits 7:0) are compared to BRKDL
1 = Low byte is not used in comparisons.
0 = R/W is not used in comparisons
1 = R/W is used in comparisons
0 = A write cycle will be matched
1 = A read cycle will be matched
0 = R/W is not used in the comparisons
1 = R/W is used in comparisons
0 = Write cycle will be matched
1 = Read cycle will be matched
Development Support
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
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