XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 281

• Manufacturer Part Number: XC68HC12A0CPV8
• Description: IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
• Manufacturer: Freescale Semiconductor

Specifications of XC68HC12A0CPV8

• Controller Family/series: 68HC12
• No. Of I/o's: 68
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Core Size: 16 Bit
• Program Memory Size: 60KB
• Peripherals: ADC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
SPIE — SPI Interrupt Enable
SPE — SPI System Enable
SWOM — Port S Wired-OR Mode
MSTR — SPI Master/Slave Mode Select
CPOL, CPHA — SPI Clock Polarity, Clock Phase
SSOE — Slave Select Output Enable
LSBF — SPI LSB First enable
When MODF is set, SPE always reads zero. SP0CR1 must be written
as part of a mode fault recovery sequence.
Controls not only SPI output pins but also the general-purpose output
pins (PS[4:7]) which are not used by SPI.
These two bits are used to specify the clock format to be used in SPI
operations. When the clock polarity bit is cleared and data is not being
transferred, the SCK pin of the master device is low. When CPOL is
set, SCK idles high. See
The SS output feature is enabled only in the master mode by
asserting the SSOE and DDS7.
0 = SPI interrupts are inhibited
1 = Hardware interrupt sequence is requested each time the SPIF
0 = SPI internal hardware is initialized and SPI system is in a low-
1 = PS[4:7] are dedicated to the SPI function
0 = SPI and/or PS[4:7] output buffers operate normally
1 = SPI and/or PS[4:7] output buffers behave as open-drain
0 = Slave mode
1 = Master mode
0 = Data is transferred most significant bit first
1 = Data is transferred least significant bit first
or MODF status flag is set
power disabled state.
outputs
Multiple Serial Interface
Figure 15-4
and
Figure
Serial Peripheral Interface (SPI)
15-5.
Multiple Serial Interface
Technical Data
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