XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 170

IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112

XC68HC12A0CPV8

Manufacturer Part Number
XC68HC12A0CPV8
Description
IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of XC68HC12A0CPV8

Controller Family/series
68HC12
No. Of I/o's
68
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
1
Core Size
16 Bit
Program Memory Size
60KB
Peripherals
ADC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Clock Functions
COPCTL — COP Control Register
Technical Data
170
RESET:
RESET:
CME
Bit 7
NOTE:
0/1
0/1
FCME
6
0
0
CME — Clock Monitor Enable
The VDDPLL-dependent reset operation is not implemented on first
pass products.
In this case the state of CME on reset is 0.
FCME — Force Clock Monitor Enable
Read and write anytime.
If FCME is set, this bit has no meaning nor effect.
On reset
Write once in normal modes, anytime in special modes. Read
anytime.
In normal modes, when this bit is set, the clock monitor function
cannot be disabled until a reset occurs.
See
0 = Clock monitor is disabled. Slow clocks and stop instruction may
1 = Slow or stopped clocks (including the stop instruction) will
0 = Clock monitor follows the state of the CME bit.
1 = Slow or stopped clocks will cause a clock reset sequence or
FCMCOP
Limp-Home and Fast STOP Recovery
5
0
0
be used.
cause a clock reset sequence or limp-home mode. See
Home and Fast STOP Recovery
CME is 1 if VDDPLL is high
CME is 0 if VDDPLL is low.
limp-home mode.
WCOP
Clock Functions
4
0
0
DISR
3
0
1
CR2
2
1
1
modes.
CR1
MC68HC912D60A — Rev. 3.1
modes.
1
1
1
Freescale Semiconductor
Bit 0
CR0
1
1
Special
Normal
Limp-
$0016

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