XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 301
![IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112](/photos/19/7/190728/4243102_sml.jpg)
XC68HC12A0CPV8
Manufacturer Part Number
XC68HC12A0CPV8
Description
IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
Manufacturer
Freescale Semiconductor
Datasheet
1.MC912D60ACFUE8.pdf
(460 pages)
Specifications of XC68HC12A0CPV8
Controller Family/series
68HC12
No. Of I/o's
68
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
1
Core Size
16 Bit
Program Memory Size
60KB
Peripherals
ADC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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SC0DRL— MI Bus Data Register Low
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Push field
Pull field
RESET:
R7/T7
Bit 7
A2
—
0
R6/T6
A1
—
6
1
RAF — Receiver Active Flag
R7T7–R0T0 — Receive/Transmit Data Bits 7 to 0
This register forms the 8-bit data/address word for the MI push field
and contains the 3-bit data word received as the MI pull field.
READ: Reads access the three bits of pull field data (stored in bits
3–1) of the read-only MI Bus receive data register. Bits [7:4, 0] are a
fixed data pattern when a valid status and end-of-frame is returned. A
valid status is represented by the following data pattern: 0101 xxx1
(bits 7–0), where ‘xxx’ is the status. All ones in the receive data
register indicate that an error occurred on the MI Bus. Bits are
received LSB first by the MCU, and the status bits map as shown in
the above table.
0 = A character is not being received
1 = A character is being received
R5/T5
A0
—
5
0
Freescale Interconnect Bus
1. 20kHz bit rate requires 25µs (40kHz) time slots.
2. 25µs ÷ 16
MDL1
R4/T4
D4
0
0
1
1
—
4
1
Table 16-1. MI Bus Delay
MDL0
R3/T3
D3
S1
—
3
0
1
0
1
Delay factor Delay time
R2/T2
D2
S2
—
2
1
2
3
4
R1/T1
S3
D1
1.5625 µs
—
1
4.6875 µs
3.125 µs
Freescale Interconnect Bus
6.25 µs
SCI0/MI Bus registers
R0/T0
(2)
Bit 0
(1)
D0
—
1
Technical Data
$00C7
301
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