XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 341
XC68HC12A0CPV8
Manufacturer Part Number
XC68HC12A0CPV8
Description
IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
Manufacturer
Freescale Semiconductor
Datasheet
1.MC912D60ACFUE8.pdf
(460 pages)
Specifications of XC68HC12A0CPV8
Controller Family/series
68HC12
No. Of I/o's
68
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
8MHz
No. Of Timers
1
Core Size
16 Bit
Program Memory Size
60KB
Peripherals
ADC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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17.13.10 msCAN12 Identifier Acceptance Control Register (CIDAC)
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
CIDAC
$0108
RESET
R
W
NOTE:
Bit 7
0
0
TXEIE2 – TXEIE0 — Transmitter Empty Interrupt Enable
The CTCR register is held in the reset state when the SFTRES bit in
CMCR0 is set.
IDAM1 – IDAM0 — Identifier Acceptance Mode
The CPU sets these flags to define the identifier acceptance filter
organisation (see
summarizes the different settings. In Filter Closed mode no
messages are accepted such that the foreground buffer is never
reloaded.
6
0
0
0 = No interrupt will be generated from this event.
1 = A transmitter empty (transmit buffer available for transmission)
event will result in a transmitter empty interrupt.
Table 17-9. Identifier Acceptance Mode Settings
IDAM1
IDAM1
5
0
0
0
1
1
MSCAN Controller
Identifier Acceptance
IDAM0
IDAM0
4
0
0
1
0
1
Four 16 bit Acceptance Filters
Identifier Acceptance Mode
Two 32 bit Acceptance Filters
Eight 8 bit Acceptance Filters
3
0
0
Programmer’s Model of Control Registers
Filter Closed
Filter).
IDHIT2
2
0
Table 17-8
IDHIT1
1
0
MSCAN Controller
Technical Data
IDHIT0
Bit 0
0
341
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