XC68HC12A0CPV8 Freescale Semiconductor, XC68HC12A0CPV8 Datasheet - Page 428

• Manufacturer Part Number: XC68HC12A0CPV8
• Description: IC, 16BIT MCU, 68HC12, 8MHZ, TQFP-112
• Manufacturer: Freescale Semiconductor

Specifications of XC68HC12A0CPV8

• Controller Family/series: 68HC12
• No. Of I/o's: 68
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Core Size: 16 Bit
• Program Memory Size: 60KB
• Peripherals: ADC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Appendix: CGM Practical Aspects
21.3.2 Operation Under Adverse Environmental Conditions
21.3.3 Filter Components Selection Guide
21.3.3.1 Equations Set
Technical Data
428
synchronizers would be jeopardized (e.g. the MCLK and XCLK clock
generators).
The normal operation for the PLL is the so-called ‘automatic bandwidth
selection mode’ which is obtained by having the AUTO bit set in the
PLLCR register. When this mode is selected and as the VCO frequency
approaches its target, the charge pump current level will automatically
switch from a relatively high value of around 40 µA to a lower value of
about 3 µA. It can happen that this low level of charge pump current is
not enough to overcome leakages present at the XFC pin due to adverse
environmental conditions. These conditions are frequently encountered
for uncoated PCBs in automotive applications. The main symptom for
this failure is an unstable characteristic of the PLL which in fact ‘hunts’
between acquisition and tracking modes. It is then advised for the
running software to place the PLL in manual, forced acquisition mode by
clearing both the AUTO and the ACQ bits in the PLLCR register. Doing
so will maintain the high current level in the charge pump constantly and
will permit to sustain higher levels of leakages at the XFC pin. This latest
revision of the Clock Generator Module maintains the lock detection
feature even in manual bandwidth control, offering then to the
application software the same flexibility for the clocking control as the
automatic mode.
These equations can be used to select a set of filter components. Two
cases are considered:
1. The ‘tracking’ mode. This situation is reached normally when the
2. The ‘acquisition’ mode. This situation is reached when the PLL
PLL operates in automatic bandwidth selection mode (AUTO=1 in
the PLLCR register).
operates in manual bandwidth selection mode and forced
Appendix: CGM Practical Aspects
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor