EWIXP420ABBT Intel, EWIXP420ABBT Datasheet - Page 19

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EWIXP420ABBT

Manufacturer Part Number
EWIXP420ABBT
Description
Manufacturer
Intel
Datasheet

Specifications of EWIXP420ABBT

Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant

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General Hardware Design Considerations—Intel
plane processors
3.0
Warning:
3.1
December 2007
Document Number: 252817-008US
General Hardware Design Considerations
This chapter contains information on how to implement and interface the SDRAMs,
flash, SRAM, Ethernet PHYs, UART and other peripherals to the Intel
Line of Network Processors and IXC1100 Control Plane Processor.
This chapter’s signal-definition tables list pull-up and pull-down resistor
recommendations that are required when the particular enabled interface is not being
used in the application. These external resistor requirements are only needed if the
particular model of Intel
Control Plane Processor has the particular interface enabled and the interface is not
required in the application.
All IXP42X product line and IXC1100 control plane processors I/O pins are not 5-V
tolerant.
Disabled features, within the IXP42X product line and IXC1100 control plane
processors, do not require external resistors as the processor will have internal pull-up
or pull-down resistors enabled as part of the disabled interface.
PC133 SDRAM Interface
The SDRAM memory controller, integrated into the IXP42X product line and IXC1100
control plane processors, supports a 32-bit data bus interface operating at 133 MHz,
eight open pages, two external banks with memory configuration from 8 to 256
Mbytes.
General SDRAM routing guidelines can be found in
Topologies” on page
Specification.
These are the features:
• Performs eight word length burst size to SDRAM
• Supports bursts up to eight words internally
• Is a target device on the Internal Buses and does not split any transactions
• Has RAS-to-CAS delay of three clocks
• Has a CAS-to-data latency of two or three clocks, as programmed by the
• Runs at 133 MHz frequency (same as the internal bus frequency)
• Maintains up to eight open pages
• Supports a total of two physical banks totaling to 8 Mbytes/256 Mbytes of memory
• Handles transactions from the internal bus in a big-endian manner
• Automatically refreshes the SDRAM devices using an internal refresh counter
configuration register
space
Intel
73. For more detailed information, see the PC133 SDRAM
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
®
IXP42X Product Line of Network Processors and IXC1100
®
IXP42X product line and IXC1100 control
Section 7.1, “PC133 SDRAM
Hardware Design Guidelines
®
IXP42X Product
19