EWIXP420ABBT Intel, EWIXP420ABBT Datasheet - Page 78

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EWIXP420ABBT

Manufacturer Part Number
EWIXP420ABBT
Description
Manufacturer
Intel
Datasheet

Specifications of EWIXP420ABBT

Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant

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Table 20.
7.2.1
7.2.2
Intel
Hardware Design Guidelines
78
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
PCI Clock Routing Guidelines
Trace Length Limits
For acceptable signal integrity with the PCI bus speeds up to 66 MHz, it is very
important to PCB design layout to have controller impedance:
For add-in cards, trace lengths from the top of the card edge connector to the
processors are:
Routing Guidelines
The recommended routing solution is to arrange the signal level layouts so that no
high-speed data bus (33 MHz) is referenced to the 3.3-V plane and 5-V plane.
Signal traces should either remain entirely over the 3.3-V or 5-V plane. Signals that
must cross from one domain to the other should be routed on the opposite side of the
board so that they are referenced to the ground plane, which is not split. If this is not
possible, signals must be routed over the plane split — the two planes capacitatively
tied together. The 5-V and 3.3-V planes should be tied together with 0.01-µF, high-
speed capacitors for each of the four signals crossing the split. The capacitor should be
placed not more that 0.25 inches from the point the signals cross the split.
• Avoid routing signals >8 inches
• The maximum trace lengths for each 32-bit interface signal from IXP42X product
• Trace lengths for the PCI clock signal from processors to PCI connector must be
• The maximum trace length for all 32-bit interface signals should not exceed 1.5
• The trace length for the PCI_CLK signal is 2.5 inches ± 0.1 inch for 32-bit cards and
Characteristic Trace Impedance
line and IXC1100 control plane processors to PCI Bus is limited to 1.5 inches for all
32-bit cards
2.5 inches ± 0.1 inches and must be routed to only one load.
inches for 32-bit cards. This includes all signals except those listed as “Signal Pins,”
“Interrupt Pins,” and “JTAG Pins,” as per PCI Local Bus Specification, Rev. 2.2.
should be routed to only a single load.
Nominal Trace Separation
Spacing to Other Groups
Intel
Reference Plane Ground
Nominal Trace Width
Maximum VIAS
Trace length A
Trace length B
®
Signal Group
Parameter
Resistor Rs
IXP42X product line and IXC1100 control plane processors—Critical Routing Topologies
Topology
Routing Guidelines
Max 11,000 mils
Point to-Point
Max 200 mils
50 Ω ± 10%
30 Ω ± 10%
PCI Clock
Ground
20 mils
4 mils
9 mils
6
Document Number: 252817-008US
December 2007