EWIXP420ABBT Intel, EWIXP420ABBT Datasheet - Page 33

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EWIXP420ABBT

Manufacturer Part Number
EWIXP420ABBT
Description
Manufacturer
Intel
Datasheet

Specifications of EWIXP420ABBT

Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant

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General Hardware Design Considerations—Intel
plane processors
3.4.1
Table 7.
December 2007
Document Number: 252817-008US
Note:
ETH_TXDATA0[3:0]
ETH_RXDATA0[3:0]
ETH_TXDATA1[3:0]
ETH_RXCLK0
ETH_TXCLK0
ETH_TXCLK1
ETH_RXDV0
ETH_TXEN0
ETH_TXEN1
ETH_MDIO
ETH_COL0
ETH_CRS0
ETH_MDC
Name
For explanations of the
Ethernet Interface Signals
Ethernet Interface Signals (Sheet 1 of 2)
Type*
I/O
I/O
O
O
O
O
I
I
I
I
I
I
I
Type
Externally supplied transmit clock.
This MAC interface does not contain hardware hashing capabilities.
Should be pulled high through a 10-kΩ resistor when not being used in the system.
Transmit data bus to PHY, asserted synchronously with respect to ETH_TXCLK0. This MAC
interface does not contain hardware hashing capabilities.
Indicates that the PHY is being presented with nibbles on the MII interface. Asserted
synchronously with respect to ETH_TXCLK0 at the first nibble of the preamble, and remains
asserted until all the nibbles of a frame are presented. This MAC interface does not contain
hardware hashing capabilities.
Externally supplied receive clock.
This MAC interface does not contain hardware hashing capabilities.
Should be pulled high through a 10-kΩ resistor when not being used in the system.
Receive data bus from PHY, data sample synchronously with respect to ETH_RXCLK0. This
MAC interface does not contain hardware hashing capabilities.
Should be pulled high through a 10-kΩ resistor when not being used in the system.
Receive data valid, used to inform the MII interface that the Ethernet PHY is sending data.
This MAC interface does not contain hardware hashing capabilities.
Should be pulled high through a 10-kΩ resistor when not being used in the system.
Asserted by the PHY when a collision is detected by the PHY. This MAC interface does not
contain hardware hashing capabilities.
Should be pulled low through a 10-kΩ resistor when not being used in the system.
Asserted by the PHY when the transmit medium or receive medium are active. De-asserted
when both the transmit medium and receive medium are idle. Remains asserted
throughout the duration of collision condition. PHY asserts CRS asynchronously and de-
asserts synchronously with respect to ETH_RXCLK0. This MAC interface does not contain
hardware hashing capabilities.
Should be pulled high through a 10-kΩ resistor when not being used in the system.
Management data output. Provides the write data to both PHY devices connected to each
MII interface.
Must be pulled high through a 1.5-kΩ resistor when connected.
Should be pulled high through a 10-kΩ resistor when not being used in the system.
Management data clock. Management data interface clock used clock the MDIO signal as an
output and sample the MDIO as an input. The ETH_MDC is an input on power up and can be
configured to be an output through an Intel API, which can be found in the Intel
Software Programmer’s Guide.
Externally supplied transmit clock.
This MAC contains hardware hashing capabilities.
Should be pulled high through a 10-kΩ resistor when not being used in the system.
Transmit data bus to PHY, asserted synchronously with respect to ETH_TXCLK1. This MAC
contains hardware hashing capabilities.
Indicates that the PHY is being presented with nibbles on the MII interface. Asserted
synchronously with respect to ETH_TXCLK1, at the first nibble of the preamble, and
remains asserted until all the nibbles of a frame are presented. This MAC contains hardware
hashing capabilities.
• 25 MHz for 100 Mbps operation
• 2.5 MHz for 10 Mbps
• 25 MHz for 100-Mbps operation
• 2.5 MHz for 10 Mbps
• 25 MHz for 100-Mbps operation
• 2.5 MHz for 10 Mbps
column abbreviations, see
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
®
IXP42X product line and IXC1100 control
Table 21 on page
Description
81.
Hardware Design Guidelines
®
IXP400
33