EWIXP420ABBT Intel, EWIXP420ABBT Datasheet - Page 79

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EWIXP420ABBT

Manufacturer Part Number
EWIXP420ABBT
Description
Manufacturer
Intel
Datasheet

Specifications of EWIXP420ABBT

Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant

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Critical Routing Topologies—Intel
7.2.3
December 2007
Document Number: 252817-008US
Signal Loading
Shared PCI signals must be limited to one load on each of the PCI slots. Any violation of
expansion board or add-on device trace length or loading limits compromises system-
signal integrity.
The PCI Local Bus Specification, Rev. 2.2 allows a maximum PCI clock skew of 2 ns
between any two devices connected on the PCI bus. (The allowable clock skew for
66 MHz is 1 ns.)
To minimize skew on the primary PCI bus, place the IXP42X product line and IXC1100
control plane processors as close as possible to the PCI edge connector. Trace length
from the PCI edge connector to the processors’ PCI_CLK input must be as short as
physically possible — the maximum length being 2.5 inches.
For the secondary PCI bus, the allowable skew is 2 ns between any device on the
secondary PCI bus. (The allowable clock skew for 66 MHz is 1 ns.) Keep these
secondary clock routes between 1.0 to 8.0 inches to provide a skew of less than 1 ns.
®
IXP42X product line and IXC1100 control plane processors
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
§ §
Hardware Design Guidelines
79