EWIXP420ABBT Intel, EWIXP420ABBT Datasheet - Page 65
Manufacturer Part Number
Specifications of EWIXP420ABBT
Core Operating Frequency
Operating Temperature (max)
Operating Temperature (min)
Operating Temperature Classification
Lead Free Status / Rohs Status
General Layout and Routing Guide—Intel
Document Number: 252817-008US
Clock Signal Considerations
• Provide return paths of board power and ground close to clock traces.
• There should be a ground plane adjacent to the layer where the clock traces are
• Keep clock traces away from the edge of the board.
• Keep clock traces away from I/O area.
• Keep clock traces away from analog signals, including voltage reference signals
• Clock signals should not cross over a split in the plane.
• Route clock signals in stripline-like structures when possible.
• Eliminate all traces and vias under crystals or oscillator circuits unless there is a
• Do not route parallel signal traces directly above or below clock traces unless there
• Select type of grounding: single-point or multi-point.
• Route clock traces with a minimum number of vias.
• Space clock traces with other signals three times the trace width on each side.
• If possible, route all clock signals in a radial manner.
If there is a power plane, instead of a ground plane, make sure that the power
plane has adequate decoupling to ground, especially at the clock drivers and
plane between the trace and the component.
is at least one ground and or power plane separation between those layers.
— Use single-point grounding for low-frequency applications (audio, etc.) with
— Use multi-point grounding for high-frequency circuits with clock rates of 1 MHz
— Option 1: Route clock over a continuous plane.
— Option 2: Provide wide Power and Ground traces next to and on upper or lower
— Do not jump layers with high-speed signals. Doing so disrupts RF coupling
— It is not necessary to put ground shield traces around the clock signals except
— Place guard traces around each and every clock trace if the board is single- or
— Do not route two different signals between the same guard traces, since
— Do not daisy-chain. Provide a series resistor for each radial trace.
— Do not use stubs or “T” connections on clock signals unless electrically short.
clock rates of 1 MHz or lower.
between the trace and the plane. Disruption prevents RF current from
completing its route uninterrupted from source to load in a continuous manner.
If traces must jump layers, use ground vias at each and every layer jump to
maintain image plane continuity.
when the clock trace is close to the edge of the board. in that case 3x trace
width distance should also be kept to ground shield to avoid lowering the
impedance of the clock trace. Crosstalk may be eliminated or reduced by guard
traces or 3x spacing. This fence should be stitched to ground through vias at
varying distances not to exceed 0.5 inches.
double-sided (no ground plane) with minimal distance between signal and the
guard trace or otherwise follow the 3x rule; this minimizes crosstalk and
provides a return path for the RF current.
crosstalk may develop. If the traces are differential, then only these two traces
may be routed with the same guard trace.
IXP42X product line and IXC1100 control plane
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Hardware Design Guidelines