EWIXP420ABBT Intel, EWIXP420ABBT Datasheet - Page 26

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EWIXP420ABBT

Manufacturer Part Number
EWIXP420ABBT
Description
Manufacturer
Intel
Datasheet

Specifications of EWIXP420ABBT

Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant

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3.2.1
Table 4.
3.2.2
Intel
Hardware Design Guidelines
26
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Expansion Bus Interface Signals
Expansion Bus Interface Signals
Configuration Straps
At power up or whenever a reset is asserted, the expansion-bus address outputs are
switched to inputs and the states of the bits are captured and stored in Configuration
Register 0, bits 23 through 0. This occurs on the first cycle after the synchronous de-
assertion of the reset signal.
These configuration bits are made available to the system through the expansion-bus
address lines. To set a bit to 0, place a 4.7-kΩ, pull-down resistor on the appropriate
address line. Weak pull-up resistors are placed on each expansion-bus address pin; so
no population is needed to set the bit to 1.
EX_CLK
EX_ALE
EX_ADDR[23:0]
EX_WR_N
EX_RD_N
EX_CS_N[7:0]
EX_DATA[15:0]
EX_IOWAIT_N
EX_RDY[3:0]
Note:
Intel
For explanations of the
Name
®
IXP42X product line and IXC1100 control plane processors—General Hardware Design
Type*
I/O
I/O
Type
O
O
O
O
I
I
I
column abbreviations, see
Input clock signal used to sample all expansion interface inputs and
clock all expansion interface outputs.
Address-latch enable used for multiplexed address/data bus
accesses. Used in Intel and Motorola* multiplexed modes of
operation.
Expansion-bus address used as an output for data accesses over the
expansion bus. Also, used as an input during reset to capture device
configuration. These signals have a weak pull-up resistor attached
internally. Based on the desired configuration, various address
signals must be tied low in order for the device to operate in the
desired mode. (For details, see the Intel
Network Processors and IXC1100 Control Plane Processor
Developer’s Manual.)
Intel-mode write strobe / Motorola-mode data strobe
(EXP_MOT_DS_N) / TI*-mode data strobe (TI_HDS1_N).
Intel-mode read strobe / Motorola-mode read-not-write
(EXPB_MOT_RNW) / TI mode read-not-write (TI_HR_W_N).
External chip selects for expansion bus.
Expansion-bus, bidirectional data
Data ready/acknowledge from expansion-bus devices. Expansion-
bus access is halted when an external device sets EX_IOWAIT_N to
logic 0 and resume from the halted location once the external device
sets EX_IOWAIT_N to logic 1. This signal affects accesses that use
EX_CS_N[7:0] when the chip select is configured in Intel- or
Motorola-mode operation.
Should be pulled high through a 10-kΩ resistor, when the signal is
not being used in the system.
HPI interface ready signals. Can be configured to be active high or
active low. These signals are used to halt accesses using chip Selects
7 through 4 when the chip selects are configured to operate in HPI
mode. There is one RDY signal per chip select. This signal only
affects accesses that use EX_CS_N[7:4].
Should be pulled high through a 10-kΩ resistor when the signal is
not being used in the system.
• Chip selects 0 through 7 can be configured to support Intel or
• Chip selects 4 through 7 can be configured to support TI HPI bus
Motorola bus cycles.
cycles.
Table 21 on page
Description
Document Number: 252817-008US
®
IXP42X Product Line of
81.
Considerations
December 2007