MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 18

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

19.3.3
19.3.4
19.3.5
19.3.6
19.3.7
19.3.8
19.3.9
19.3.10
19.3.11
19.3.12
19.3.13
19.3.14
19.3.14.1
19.3.14.2
20.1
20.1.1
20.2
20.2.1
20.2.2
20.2.2.1
20.2.2.2
20.2.2.3
20.2.2.4
20.2.2.5
20.2.2.6
20.2.2.7
20.3
20.3.1
20.3.2
20.4
20.4.1
20.5
20.5.1
20.5.2
20.5.3
20.6
20.6.1
xviii
Paragraph
Number
Introduction ................................................................................................................... 20-1
Overview ....................................................................................................................... 20-4
Features ......................................................................................................................... 20-9
Modes of Operation .................................................................................................... 20-12
External Signal Description ........................................................................................ 20-13
Memory Map/Register Definition .............................................................................. 20-14
Microcontroller Initialization .................................................................................. 19-36
User Initialization (After Asserting ECRn[ETHER_EN]) ..................................... 19-37
Network Interface Options ...................................................................................... 19-37
FEC Frame Transmission ....................................................................................... 19-38
FEC Frame Reception ............................................................................................. 19-39
Ethernet Address Recognition ................................................................................ 19-40
Hash Algorithm ....................................................................................................... 19-43
Block Diagram .......................................................................................................... 20-3
eTPU Operation Overview ....................................................................................... 20-5
eTPU Engine ............................................................................................................. 20-5
eTPU Feature Summary ............................................................................................ 20-9
eTPU Enhancements over TPU3 ............................................................................ 20-11
eTPU Mode Selection ............................................................................................. 20-12
Input and Output Channel Signals (TPUCH[31:0] ................................................. 20-13
Time Base Clock Signal (TCRCLK) ...................................................................... 20-13
Channel Output Disable Signals (LTPUODIS, UTPUODIS) ................................ 20-13
Memory Map .......................................................................................................... 20-14
Full Duplex Flow Control ...................................................................................... 19-46
Inter-Packet Gap (IPG) Time ................................................................................. 19-47
Collision Handling ................................................................................................. 19-47
Internal and External Loopback ............................................................................. 19-47
Ethernet Error-Handling Procedure ....................................................................... 19-48
Time Bases ............................................................................................................ 20-6
eTPU Timer Channels .......................................................................................... 20-6
Host Interface ........................................................................................................ 20-7
Shared Data memory (SDM) ................................................................................ 20-7
Scheduler .............................................................................................................. 20-8
Microengine .......................................................................................................... 20-8
Debug Interface .................................................................................................... 20-9
Transmission Errors ........................................................................................... 19-48
Reception Errors ................................................................................................ 19-49
Enhanced Time Processing Unit (eTPU)
MCF5235 Reference Manual, Rev. 2
Contents
Chapter 20
Title
Freescale Semiconductor
Number
Page