MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 31

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Freescale Semiconductor
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chapter describes the programming model and signal timing, as well as the command set
required for synchronous operations.
Chapter 19, “Fast Ethernet Controllers (FEC0 &
a functional block diagram, and transceiver connection information for both MII (Media
Independent Interface) and 7-wire serial interfaces. It also provides describes operation and
the programming model.
Chapter 20, “Enhanced Time Processing Unit (eTPU),”
featured on the MCF5235 microcontroller.
Chapter 21, “FlexCAN,”
network (CAN) protocol. This chapter describes FlexCAN module operation and provides
a programming model.
Chapter 22, “Watchdog Timer
operation in low power mode.
Chapter 23, “Programmable Interrupt Timer Modules
functionality of the four PIT timers, including operation in low power mode.
Chapter 24, “DMA Timers
of the four DMA timer modules (DTIM0, DTIM1, DTIM2, and DTIM3). These 32-bit
timers provide input capture and reference compare capabilities with optional signaling of
events using interrupts or triggers. This chapter also provides programming examples.
Chapter 25, “Queued Serial Peripheral Interface (QSPI)
overview and a description of operation, including details of the QSPI’s internal storage
organization. The chapter concludes with the programming model and a timing diagram.
Chapter 26, “UART
receiver/transmitters (UARTs) implemented on the MCF5235 and includes programming
examples.
Chapter 27, “I2C
clock synchronization, and I
programming examples.
Chapter 28, “Message Digest Hardware Accelerator
of two of the world’s most popular cryptographic hash functions: SHA-1 and MD5.
Accelerators for either algorithm separately have been designed, however the MDHA
combines similar functions of the two algorithms into one small, optimized area of silicon
on the MCF5235 device.
Chapter 29, “Random Number Generator (RNG),”
Generator (RNG), including a programming model, functional description, and application
information.
Chapter 30, “Symmetric Key Hardware Accelerator (SKHA),”
hardware coprocessor designed to implement two widely used symmetric key block cipher
algorithms, AES and DES.
Interface,” describes the MCF5235 I
Modules,” describes the use of the universal asynchronous
describes the MCF5235 implementation of the controller area
MCF5235 Reference Manual, Rev. 2
(DTIM0–DTIM3),” describes the configuration and operation
2
C programming model registers. It also provides extensive
Module,” describes Watchdog timer functionality, including
FEC1),” provides a feature-set overview,
describes the 32-bit Random Number
(MDHA),” describes implementation
(PIT0–PIT3),” describes the
2
C module, including I
describes the new time unit
Module,” provides a feature-set
describes the cryptographic
2
C protocol,
Organization
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