MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 466

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

FlexCAN
21.3.2.3 FlexCAN Free Running Timer Register (TIMERn)
This register represents a 16-bit free running counter that can be read and written to by the CPU.
The timer starts from 0x0000 after reset, counts linearly to 0xFFFF, and wraps around.
The timer is clocked by the FlexCAN bit-clock (which defines the baud rate on the CAN bus).
During a message transmission/reception, it increments by one for each bit that is received or
transmitted. When there is no message on the bus, it counts using the previously programmed baud
rate. During freeze mode, the timer is not incremented.
The timer value is captured at the beginning of the identifier (ID) field of any frame on the CAN
bus. This captured value is written into the TIMESTAMP entry in a message buffer after a
successful reception or transmission of a message.
Writing to the timer is an indirect operation. The data is first written to an auxiliary register and
then an internal request/acknowledge procedure across clock domains is executed. All this is
transparent to the user, except for the fact that the data will take some time to be actually written
to the register. If desired, software can poll the register to discover when the data was actually
written.
21.3.2.4 Rx Mask Registers (RXGMASKn, RX14MASKn, RX15MASKn)
These registers are used as acceptance masks for received frame IDs. Three masks are defined: A
global mask (RXGMASKn) used for Rx buffers 0–13 and two separate masks for buffers 14
(RX14MASKn) and 15 (RX15MASKn). The meaning of each mask bit is the following:
MIn bit = 0: The corresponding incoming ID bit is “don’t care”.
MIn bit = 1: The corresponding ID bit is checked against the incoming ID bit, to see if a match
exists.
Note that these masks are used both for Standard and Extended ID formats. The value of the mask
registers should not be changed while in normal operation (only while in freeze mode), as locked
21-12
Reg Addr
Reset
Reset
W
W
R
R
31
15
0
0
0
30
14
0
0
0
Figure 21-6. FlexCAN Timer Register (TIMERn)
29
13
0
0
0
28
12
0
0
0
IPSBAR + 0x1C_0008 (CAN0); 0x1F_0008 (CAN1)
MCF5235 Reference Manual, Rev. 2
27
11
0
0
0
26
10
0
0
0
25
0
0
0
9
24
0
0
8
0
TIMER
23
0
0
0
7
22
0
0
0
6
21
0
0
0
5
20
0
0
0
4
19
0
0
0
3
Freescale Semiconductor
18
0
0
2
0
17
0
0
0
1
16
0
0
0
0