MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 445

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

20.6.2.3.6 eTPU Channel Data Transfer Request Enable Register (ETPU_CDTRER)
Data transfer request enable status bits from all channels are grouped in ETPU_CDTRER. The bits
are mirrored in the channels’ configuration registers. For more on configuration registers and data
transfer request enable, refer to
(ETPU_CnCR),” and the eTPU User’s Manual.
20.6.2.3.7 eTPU Channel Pending Service Status Register (ETPU_CPSSR)
ETPU_CPSSR is a read-only register that holds the status of the pending channel service requests.
For information on channel service requests, refer to the eTPU User’s Manual.
Freescale Semiconductor
Figure 20-15. eTPU Channel Data Transfer Request Enable Register (ETPU_CDTRER)
Address
31–0
31–0
Bits
Bits
Reset
Reset
W
W
R
R
31
16
More than one source may be requesting service when a channel’s
service request bit is set.
0
0
DTREn
Name
Name
CIEn
30
17
0
0
Table 20-15. ETPU_CDTRER Field Descriptions
29
18
0
0
Table 20-14. ETPU_CIER Field Descriptions
Channel n interrupt enable. Enable the eTPU channels to interrupt the MCF5235 ColdFire
core.
0 Interrupt disabled for channel n.
1 Interrupt enabled for channel n
For details about interrupts refer to the eTPU User’s Manual.
Channel n data transfer request enable. Enable data transfer requests for their respective
channels.
0 Data transfer request disabled for channel n.
1 Data transfer request enabled for channel n.
For details about interrupts refer to the eTPU User’s Manual.
28
19
0
0
MCF5235 Reference Manual, Rev. 2
Section 20.6.2.4.2, “eTPU Channel n Configuration Register
27
20
0
0
26
21
0
0
IPSBAR + 0x1D_0250
25
22
0
0
NOTE
24
23
0
0
DTRE
DTRE
Description
Description
23
24
0
0
22
25
0
0
21
26
0
0
20
27
0
0
Memory Map/Register Definition
19
28
0
0
18
29
0
0
17
30
0
0
16
31
0
0
20-31