MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 655

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Table 32-8
Freescale Semiconductor
DRc[4–0]
Reset
Reset
31–28
23–20
19–17
Bit
27
26
25
24
16
W
W
R
R MAP TRC EMU
describes CSR fields.
31
15
0
0
BSTAT
Name
BKPT
HALT
FOF
TRG
HRL
IPW
30
14
0
0
—
BSTAT
Figure 32-6. Configuration/Status Register (CSR)
29
13
0
0
Breakpoint status. Provides read-only status information concerning hardware
breakpoints. BSTAT is cleared by a TDR write or by a CSR read when either a level-2
breakpoint is triggered or a level-1 breakpoint is triggered and the level-2 breakpoint is
disabled.
0000 No breakpoints enabled
0001 Waiting for level-1 breakpoint
0010 Level-1 breakpoint triggered
0101 Waiting for level-2 breakpoint
0110 Level-2 breakpoint triggered
Fault-on-fault. If FOF is set, a catastrophic halt occurred and forced entry into BDM. FOF
is cleared whenever CSR is read.
Hardware breakpoint trigger. If TRG is set, a hardware breakpoint halted the processor
core and forced entry into BDM. Reset, the debug
TRG.
Processor halt. If HALT is set, the processor executed a HALT and forced entry into BDM.
Reset, the debug
Breakpoint assert. If BKPT is set, BKPT was asserted, forcing the processor into BDM.
Reset, the debug
Hardware revision level. Indicates the level of debug module functionality. An emulator
could use this information to identify the level of functionality supported.
0000 Initial debug functionality (Revision A) .
0001–1111 Reserved
Reserved, should be cleared.
Inhibit processor writes. Setting IPW inhibits processor-initiated writes to the debug
module’s programming model registers. IPW can be modified only by commands from the
external development system.
28
12
0
0
Table 32-8. CSR Field Descriptions
DDC
FOF TRG HALT BKPT
27
11
0
0
MCF5235 Reference Manual, Rev. 2
UHE
GO
GO
26
10
0
0
command, or reading CSR will clear HALT.
command, or reading CSR will clear BKPT.
25
0
0
9
BTB
24
0
0
8
0x00
Description
23
0
7
0
0
NPL
22
0
0
6
HRL
GO
IPI
21
0
0
5
command, or reading CSR will clear
SSM
20
0
0
4
Memory Map/Register Definition
19
0
0
0
0
3
18
0
0
0
0
2
17
0
0
0
0
1
IPW
16
0
0
0
0
32-11