MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 452

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Enhanced Time Processing Unit (eTPU)
20.6.2.4.4 eTPU Channel n Host Service Request Register (ETPU_CnHSRR)
ETPU_CnHSRR is used by the MCF5235 ColdFire core to issue service requests to the channel.
20-38
21–16
12–2
Bits
1–0
22
15
14
13
DTROS
DTROC
Table 20-21. ETPU_CnSCR Field Descriptions (Continued)
Name
Read:
Write:
OPS
OBE
IPS
FM
—
—
Data transfer request overflow status.
0 Data transfer request overflow negated for this channel.
1 Data transfer request overflow asserted for this channel.
DTROS and DTROC are mirrored in the ETPU_CDTROSR. See
“eTPU Channel Data Transfer Request Overflow Status Register
and the eTPU User’s Manual for more information on ETPU_CDTROSR and data transfer
overflows.
Data transfer request overflow clear.
0 Keep status bit unaltered.
1 Clear status bit.
DTROS and DTROC are mirrored in the ETPU_CDTROSR. See
“eTPU Channel Data Transfer Request Overflow Status Register
and the eTPU User’s Manual for more information on ETPU_CDTROSR and data transfer
overflows.
Reserved.
Channel input pin state. Shows the current value of the filtered channel input signal state
Channel output pin state. Shows the current value driven in the channel output signal,
including the effect of the external output disable feature. Since the channel input and
output signals are connected to the same pin, OPS reflects the value driven to the pin (if
OBE = 1). This is not necessarily the actual pin value, which drives the value in the IPS bit.
Output Buffer Enable. This bit shows the state of the channel output buffer enable signal,
controlled by microcode.
0 Selected channel pin operates as an input.
1 Selected channel pin operates as an output.
Reserved.
Channel function mode. Each function may use this field for specific configuration. These
bits can be tested by microengine code.
These bits are equivalent to the TPU/TPU2/TPU3 host sequence (HSQ) bits.
MCF5235 Reference Manual, Rev. 2
Description
Section 20.6.2.3.4,
(ETPU_CDTROSR).”
Section 20.6.2.3.4,
(ETPU_CDTROSR).”
Freescale Semiconductor