MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 691

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Exception ProcessingPST = 0xC,{PST = 0xB,DD = destination},// stack frame
The PST/DDATA specification for the reset exception is shown below:
Exception ProcessingPST = 0xC,
The initial references at address 0 and 4 are never captured nor displayed since these accesses are
treated as instruction fetches.
For all types of exception processing, the PST = 0xC value is driven at all times, unless the PST
output is needed for one of the optional marker values or for the taken branch indicator (0x5).
Freescale Semiconductor
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For JMP and JSR instructions, the optional target instruction address is displayed only for those effective address
fields defining variant addressing modes. This includes the following <ea>x values: (An), (d16,An), (d8,An,Xi),
(d8,PC,Xi).
For Move Multiple instructions (MOVEM), the processor automatically generates line-sized transfers if the operand
address reaches a 0-modulo-16 boundary and there are four or more registers to be transferred. For these line-sized
transfers, the operand data is never captured nor displayed, regardless of the CSR value.
The automatic line-sized burst transfers are provided to maximize performance during these sequential memory
access operations.
During normal exception processing, the PST output is driven to a 0xC indicating the exception processing state. The
exception stack write operands, as well as the vector read and target address of the exception handler may also be
displayed.
Table 32-23. PST/DDATA Specification for User-Mode Instructions (Continued)
Instruction
wddata.w
wddata.b
wddata.l
subq.l
subx.l
subi.l
swap
sub.l
tst.w
trapf
tst.b
unlk
trap
tst.l
PST = 0x5,{PST = [0x9AB],DD = target}// handler PC
PST = 0x5,{PST = [0x9AB],DD = target} // handler PC
{PST = 0xB,DD = destination},// stack frame
{PST = 0xB,DD = source},// vector read
Operand Syntax
#imm,<ea>x
Dy,<ea>x
#imm,Dx
<ea>x
<ea>x
<ea>x
<ea>y
<ea>y
<ea>y
Dy,Dx
#imm
Dx
Ax
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1
PST = 0x1, {PST = 0x8, DD = source operand}
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0x9, DD = source operand}
PST = 0x1, {PST = 0xB, DD = destination operand}
PST = 0x4, {PST = 0x8, DD = source operand
PST = 0x4, {PST = 0xB, DD = source operand
PST = 0x4, {PST = 0x9, DD = source operand
MCF5235 Reference Manual, Rev. 2
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PST/DDATA
Processor Status, DDATA Definition
32-47