MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 468

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

FlexCAN
21.3.2.5 FlexCAN Error Counter Register (ERRCNTn)
This register has two 8-bit fields reflecting the value of two FlexCAN error counters: transmit error
counter (TXECTR) and receive error counter (RXECTR). The rules for increasing and decreasing
these counters are described in the CAN protocol and are completely implemented in the FlexCAN
module. Both counters are read-only except in freeze mode, where they can be written by the CPU.
Writing to the ERRCNTn register while in freeze mode is an indirect operation. The data is first
written to an auxiliary register and then an internal request/acknowledge procedure across clock
domains is executed. All this is transparent to the user, except for the fact that the data will take
some time to be actually written to the register. If desired, software can poll the register to discover
when the data was actually written.
FlexCAN responds to any bus state as described in the protocol, e.g. transmit error-active or
error-passive flag, delay its transmission start time (error-passive), and avoid any influence on the
bus when in bus off state. The following are the basic rules for FlexCAN bus state transitions.
21-14
Figure 21-7. FlexCAN Rx Mask Registers (RXGMASKn, RX14MASKn, RX15MASKn)
• If the value of TXECTR or RXECTR increases to be greater than or equal to 128, the
Reg Addr
31–29
28–18
17–0
FLTCONF field in the error and status register (ERRSTATn) is updated to reflect
error-passive state.
Bits
Reset
Reset
W
W
R
R
31
15
0
0
1
MI28–MI18 Standard ID mask bits. These bits are the same mask bits for the Standard and Extended
MI17–MI0
Name
—
30
14
0
0
1
29
13
0
0
1
Reserved, should be cleared.
Formats.
Extended ID mask bits. These bits are used to mask comparison only in Extended Format.
Table 21-5. RXxxMASKn Field Descriptions
RX14MASKn: IPSBAR + 0x1C_0014 (CAN0); 0x1F_0014 (CAN1)
RX15MASKn: IPSBAR + 0x1C_0018 (CAN0); 0x1F_0018 (CAN1)
RXGMASKn: IPSBAR + 0x1C_0010 (CAN0); 0x1F_0010 (CAN1)
28
12
1
1
MCF5235 Reference Manual, Rev. 2
27
11
1
1
26
10
1
1
Extended ID = MI[17:0]
25
1
1
9
Standard ID = MI[28:18]
24
MI[28:0]
1
1
8
MI[28:0]
Description
23
1
7
1
22
1
1
6
21
1
1
5
20
1
1
4
19
1
1
3
Freescale Semiconductor
18
1
1
2
17
1
1
1
16
1
0
1