MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 687

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

While operating in emulation mode, the processor exhibits the following properties:
The RTE instruction exits emulation mode. The processor status output port provides a unique
encoding for emulator mode entry (0xD) and exit (0x7).
32.6.2
The debug module supports concurrent operation of both the processor and most BDM commands.
BDM commands may be executed while the processor is running, except those following
operations that access processor/memory registers:
For BDM commands that access memory, the debug module requests the processor’s local bus.
The processor responds by stalling the instruction fetch pipeline and waiting for current bus
activity to complete before freeing the local bus for the debug module to perform its access. After
the debug module bus cycle, the processor reclaims the bus.
Breakpoint registers must be carefully configured in a development system if the processor is
executing. The debug module contains no hardware interlocks, so TDR should be disabled while
breakpoint registers are loaded, after which TDR can be written to define the exact trigger. This
prevents spurious breakpoint triggers.
Because there are no hardware interlocks in the debug unit, no BDM operations are allowed while
the CPU is writing the debug’s registers (DSCLK must be inactive).
Note that the debug module requires the use of the internal bus to perform BDM commands. In
Revision A of the ColdFire Debug Module, if the processor is executing a tight loop that is
Freescale Semiconductor
• Setting CSR[EMU] forces the processor into emulator mode. EMU is examined only if
• A debug interrupt always puts the processor in emulation mode when debug interrupt
• Setting CSR[TRC] forces the processor into emulation mode when trace exception
• All interrupts are ignored, including level-7 interrupts.
• If CSR[MAP] = 1, all caching of memory and the SRAM module are disabled. All memory
• Read/write address and data registers
• Read/write control registers
RSTI is negated and the processor begins reset exception processing. It can be set while the
processor is halted before reset exception processing begins. See
Halt.”
exception processing begins.
processing begins.
accesses are forced into a specially mapped address space signaled by TT = 0x2, TM = 0x5
or 0x6. This includes stack frame writes and the vector fetch for the exception that forced
entry into this mode.
Concurrent BDM and Processor Operation
MCF5235 Reference Manual, Rev. 2
Section 32.5.1, “CPU
Real-Time Debug Support
32-43