MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 297

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

A read/write transfer reads bytes from the source address and writes them to the destination
address. The number of bytes is the larger of the sizes specified by DCRn[SSIZE] and
DCRn[DSIZE]. See
Source and destination address registers (SARn and DARn) can be programmed in the DCRn to
increment at the completion of a successful transfer. BCRn decrements when an address transfer
write completes for a single-address access (DCRn[SAA] = 0) or when SAA = 1.
14.4.1 Transfer Requests (Cycle-Steal and Continuous Modes)
The DMA channel supports internal and external requests. A request is issued by setting
DCRn[START] or by asserting DREQn or an eTPU request. Setting DCRn[EEXT] enables
recognition of external or eTPU DMA requests. Selecting between cycle-steal and continuous
modes minimizes bus usage for either internal or external requests.
14.4.2 Dual-Address Data Transfer Mode
Each channel supports dual-address transfers. Dual-address transfers consist of a source data read
and a destination data write. The DMA controller module begins a dual-address transfer sequence
during a DMA request. If no error condition exists, DSRn[REQ] is set.
Freescale Semiconductor
• Cycle-steal mode (DCRn[CS] = 1)—Only one complete transfer from source to destination
• Continuous mode (DCRn[CS] = 0)—After an internal or external request, the DMA
• Dual-address read—The DMA controller drives the SARn value onto the internal address
occurs for each request. If DCRn[EEXT] is set, a request can be either internal or external.
An internal request is selected by setting DCRn[START]. An external request is initiated
by asserting DREQn while DCRn[EEXT] is set. Note that multiple transfers will occur if
DREQn is continuously asserted.
continuously transfers data until BCRn reaches zero or a multiple of DCRn[BWC] or until
DSRn[DONE] is set. If BCRn is a multiple of BWC, the DMA request signal is negated
until the bus cycle terminates to allow the internal arbiter to switch masters. DCRn[BWC]
= 000 specifies the maximum transfer rate; other values specify a transfer rate limit.
The DMA performs the specified number of transfers, then relinquishes bus control. The
DMA negates its internal bus request on the last transfer before BCRn reaches a multiple
of the boundary specified in BWC. On completion, the DMA reasserts its bus request to
regain mastership at the earliest opportunity. The DMA loses bus control for a minimum of
one bus cycle.
bus. If DCRn[SINC] is set, the SARn increments by the appropriate number of bytes upon
a successful read cycle. When the appropriate number of read cycles complete (multiple
reads if the destination size is larger than the source), the DMA initiates the write portion
of the transfer.
If a termination error occurs, DSRn[BES,DONE] are set and DMA transactions stop.
Section 14.3.5, “DMA Control Registers
MCF5235 Reference Manual, Rev. 2
(DCR0–DCR3).”
Functional Description
14-13