MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 522

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Queued Serial Peripheral Interface (QSPI) Module
Adequate delay between transfers must be specified for long data streams because the QSPI
module requires time to load a transmit RAM entry for transfer. Receiving devices need at least
the standard delay between successive transfers. If the internal bus clock is operating at a slower
rate, the delay between transfers must be increased proportionately.
25.2.4 Transfer Length
There are two transfer length options. The user can choose a default value of 8 bits or a
programmed value of 8 to 16 bits. The programmed value must be written into QMR[BITS]. The
command RAM bits per transfer enable field, QCR[BITSE], determines whether the default value
(BITSE = 0) or the BITS[3–0] value (BITSE = 1) is used. QMR[BITS] gives the required number
of bits to be transferred, with 0b0000 representing 16.
25.2.5 Data Transfer
Operation is initiated by setting QDLYR[SPE]. Shortly after QDLYR[SPE] is set, the QSPI
executes the command at the command RAM address pointed to by QWR[NEWQP]. Data at the
pointer address in transmit RAM is loaded into the data serializer and transmitted. Data that is
simultaneously received is stored at the pointer address in receive RAM.
When the proper number of bits has been transferred, the QSPI stores the working queue pointer
value in QWR[CPTQP], increments the working queue pointer, and loads the next data for transfer
from the transmit RAM. The command pointed to by the incremented working queue pointer is
executed next unless a new value has been written to QWR[NEWQP]. If a new queue pointer
value is written while a transfer is in progress, then that transfer is completed normally.
When the CONT bit in the command RAM is set, the QSPI_CS signals are asserted between
transfers. When CONT is cleared, QSPI_CS[3:0] are negated between transfers. The QSPI_CS
signals are not high impedance.
When the QSPI reaches the end of the queue, it asserts the SPIF flag, QIR[SPIF]. If QIR[SPIFE]
is set, an interrupt request is generated when QIR[SPIF] is asserted. Then the QSPI clears
QDLYR[SPE] and stops, unless wraparound mode is enabled.
Wraparound mode is enabled by setting QWR[WREN]. The queue can wrap to pointer address
0x0, or to the address specified by QWR[NEWQP], depending on the state of QWR[WRTO].
In wraparound mode, the QSPI cycles through the queue continuously, even while requesting
interrupt service. QDLYR[SPE] is not cleared when the last command in the queue is executed.
New receive data overwrites previously received data in the receive RAM. Each time the end of
the queue is reached, QIR[SPIFE] is set. QIR[SPIF] is not automatically reset. If interrupt driven
QSPI service is used, the service routine must clear QIR[SPIF] to abort the current request.
Additional interrupt requests during servicing can be prevented by clearing QIR[SPIFE].
MCF5235 Reference Manual, Rev. 2
25-8
Freescale Semiconductor