MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 490

MOD5234 10/100 ETHERNET MODULE

MOD5234-100IR

Manufacturer Part Number
MOD5234-100IR
Description
MOD5234 10/100 ETHERNET MODULE
Manufacturer
NetBurner Inc
Type
Controllers & Processorsr

Specifications of MOD5234-100IR

Interface
I²C, SPI, UART
Voltage - Supply
2.5V
Mounting Type
Surface Mount
Package / Case
Module
Product
Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Format
-
Baud Rates
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
Q4483564
Watchdog Timer Module
22.1.2 Block Diagram
22.2
This subsection describes the memory map and registers for the watchdog timer. The watchdog
timer has a IPSBAR offset for base address of 0x14_0000. Refer to
the watchdog memory map.
22.2.1 Register Description
The watchdog timer programming model consists of these registers:
22-2
1
• Watchdog control register (WCR), which configures watchdog timer operation
• Watchdog modulus register (WMR), which determines the timer modulus
• Watchdog count register (WCNTR), which provides visibility to the watchdog counter
IPSBAR Offset
S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to
supervisor only addresses have no effect and result in a cycle termination transfer error.
0x14_0000
0x14_0004
reload value
value
Memory Map/Register Definition
Internal Bus
Clock
Watchdog Count Register (WCNTR)
Watchdog Control Register (WCR)
Table 22-2. Watchdog Timer Module Memory Map
[31:24]
Figure 22-1. Watchdog Timer Block Diagram
Divide by
HALTED
DOZE
WAIT
4096
EN
16-bit WCNTR
MCF5235 Reference Manual, Rev. 2
[23:16]
16-bit Watchdog Counter
Internal Bus
Internal Bus
16-bit WMR
Watchdog Modulus Register (WMR)
Watchdog Service Register (WSR)
[15:8]
Load Counter
16-bit WSR
Count = 0
Table 22-2
[7:0]
Freescale Semiconductor
Reset
for an overview of
Access
S/U
S
1

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