MOD5234-100IR NetBurner Inc, MOD5234-100IR Datasheet - Page 282

• Manufacturer Part Number: MOD5234-100IR
• Description: MOD5234 10/100 ETHERNET MODULE
• Manufacturer: NetBurner Inc
• Type: Controllers & Processorsr

Specifications of MOD5234-100IR

• Interface: I²C, SPI, UART
• Voltage - Supply: 2.5V
• Mounting Type: Surface Mount
• Package / Case: Module
• Product: Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Format: -
• Baud Rates: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q4483564

Interrupt Controller Modules
13.2.1.7 Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK)
The eight IACK registers can be explicitly addressed via the CPU, or implicitly addressed via a
processor-generated interrupt acknowledge cycle during exception processing. In either case, the
interrupt controller’s actions are very similar.
First, consider an IACK cycle to a specific level: that is, a level-n IACK. When this type of IACK
arrives in the interrupt controller, the controller examines all the currently-active level n interrupt
requests, determines the highest priority within the level, and then responds with the unique vector
number corresponding to that specific interrupt source. The vector number is supplied as the data
for the byte-sized IACK read cycle. In addition to providing the vector number, the interrupt
controller also loads the level and priority number for the level into the IACKLPR register, where
it may be retrieved later.
This interrupt controller design also supports the concept of a software IACK. A software IACK
is a useful concept that allows an interrupt service routine to determine if there are other pending
interrupts so that the overhead associated with interrupt exception processing (including machine
state save/restore functions) can be minimized. In general, the software IACK is performed near
the end of an interrupt service routine, and if there are additional active interrupt sources, the
current interrupt service routine (ISR) passes control to the appropriate service routine, but without
taking another interrupt exception.
When the interrupt controller receives a software IACK read, it returns the vector number
associated with the highest level, highest priority unmasked interrupt source for that interrupt
controller. The IACKLPR register is also loaded as the software IACK is performed. If there are
no active sources, the interrupt controller returns an all-zero vector as the operand. For this
situation, the IACKLPR register is also cleared.
In addition to the software IACK registers within each interrupt controller, there are global
software IACK registers. A read from the global SWIACK will return the vector number for the
highest level and priority unmasked interrupt source from all interrupt controllers. A read from one
of the LnIACK registers will return the vector for the highest priority unmasked interrupt within
a level for all interrupt controllers.
13-18
Sourc
60–63
e
Modul
e
Table 13-14. Interrupt Source Assignment for INTC1 (Continued)
Flag
Source Description
MCF5235 Reference Manual, Rev. 2
Not used
Flag Clearing Mechanism
Freescale Semiconductor