LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 1050

• Manufacturer Part Number: LPC1857FET256,551
• Description: IC MCU 32BIT 1MB FLASH 256LBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1857FET256,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
42.7.4.7 EMC data out delay register
Table 971. EMC chip select delay register (EMCCSDELAY, address 0x4008 6D08) bit
This register provides a programmable delay for the EMC DQM and EMC data outputs (8
data lanes per delay control). The delay for each control output is approximately 0.5 ns 
XXX_DELAY. (XXX_DELAY = 0x0: delay  0 ns, 0x1: delay  0.5 ns, ..., 0x7: delay 
3.5 ns.)
Table 972. EMC data out delay register (EMCDOUTDELAY, address 0x4008 6D0C) bit
Bit
2:0
3
6:4
7
10:8
11
14:12
15
18:16
19
22:20
23
26:24
27
30:28
31
Bit
2:0
3
6:4
7
10:8
11
14:12
15
18:16
19
22:20
23
26:24
Symbol
DYCS0_DELAY
-
DYCS1_DELAY
-
DYCS2_DELAY
-
DYCS3_DELAY
-
CS0_DELAY
-
CS1_DELAY
-
CS2_DELAY
-
CS3_DELAY
-
Symbol
DQM0_DELAY Delay of the EXTBUS_DQM0 output.
-
DQM1_DELAY Delay of the EXTBUS_DQM1 output.
-
DQM2_DELAY Delay of the EXTBUS_DQM2 output.
-
DQM3_DELAY Delay of the EXTBUS_DQM3 output.
-
D0_DELAY
-
D1_DELAY
-
D2_DELAY
description
description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Reserved.
Reserved.
Reserved.
Reserved.
Delay of the EXTBUS_D0 to EXTBUS_D7 outputs.
Reserved.
Delay of the EXTBUS_D8 to EXTBUS_D15 outputs.
Reserved.
Delay of the EXTBUS_D16 to EXTBUS_D23 outputs. 0
Description
Delay of the EXTBUS_DYCS0 output.
Reserved.
Delay of the EXTBUS_DYCS1 output.
Reserved.
Delay of the EXTBUS_DYCS2 output.
Reserved.
Delay of the EXTBUS_DYCS3 output.
Reserved.
Delay of the EXTBUS_CS0 output.
Reserved.
Delay of the EXTBUS_CS1 output.
Reserved.
Delay of the EXTBUS_CS2 clock enable output.
Reserved.
Delay of the EXTBUS_CS3 clock enable output.
Reserved.
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
0
0
0
0
Reset
value
-
-
-
-
0
-
0
-
0
-
0
-
Reset
value
0
-
0
-
0
-
0
-
0
-
0
-
1050 of 1164
Access
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
-
R/W
R/W
R/W
R/W
Access
R/W
-
R/W
-
-
-
-
-
R/W