LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 937
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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41.7 Debug memory re-mapping
41.8 JTAG TAP Identification
<Document ID>
User manual
During a debugging session, the System Tick Timer and the Repetitive Interrupt Timers
are automatically stopped whenever the CPU is stopped. Other peripherals are not
affected. If the Repetitive Interrupt Timer is configured such that its PCLK rate is lower
than the CPU clock rate, the RIT may not increment predictably during some debug
operations, such as single stepping.
Debugging is disabled if code read protection is enabled.
Following chip reset, a portion of the Boot ROM is mapped to address 0 so that it will be
automatically executed. The Boot ROM switches the map to point to <tbd>. In this way a
user normally does not need to know that this re-mapping occurs.
However, when a debugger halts CPU execution immediately following reset, the Boot
ROM is still mapped to address 0 and can cause confusion. Ideally, the debugger should
correct the mapping automatically in this case, so that a user does not need to deal with it.
The JTAG TAP controller contains device ID that can be used by debugging software to
identify the general type of device. <tbd>
All information provided in this document is subject to legal disclaimers.
Chapter 41: LPC18xx JTAG, Serial Wire Debug (SWD), and trace
Rev. 00.13 — 20 July 2011
UM10430
© NXP B.V. 2011. All rights reserved.
937 of 1164
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