LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 653
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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User manual
26.7.9.5 MCPWM Interrupt Flags set address
Table 565. MCPWM Interrupt flags read address (INTF - 0x400A 0068) bit description
Writing one(s) to this write-only address sets the corresponding bit(s) in INTF, thus
possibly simulating hardware interrupt(s).
Table 566. MCPWM Interrupt Flags set address (INTF_SET - 0x400A 006C) bit description
Bit
8
9
10
14:11 -
15
31:16 -
Bit
0
1
2
3
4
5
6
7
Symbol
ILIM2_F
IMAT2_F
ICAP2_F
ABORT_F
Symbol
ILIM0_F_SET
IMAT0_F_SET
ICAP0_F_SET
-
ILIM1_F_SET
IMAT1_F_SET
ICAP1_F_SET
-
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
0
1
Rev. 00.13 — 20 July 2011
Description
Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.
Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.
Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.
Reserved.
Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.
Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.
Writing a one sets the corresponding bit in the INTF register,
thus possibly simulating hardware interrupt.
Reserved.
Limit interrupt flag for channel 2.
This interrupt source is not contributing to the MCPWM
interrupt request.
If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.
Match interrupt flag for channel 2.
This interrupt source is not contributing to the MCPWM
interrupt request.
If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.
Capture interrupt flag for channel 2.
This interrupt source is not contributing to the MCPWM
interrupt request.
If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.
Reserved.
Fast abort interrupt flag.
This interrupt source is not contributing to the MCPWM
interrupt request.
If the corresponding bit in INTEN is 1, the MCPWM module is
asserting its interrupt request to the Interrupt Controller.
Reserved.
Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM)
UM10430
© NXP B.V. 2011. All rights reserved.
653 of 1164
Reset
value
-
-
-
-
-
-
-
-
Reset
value
0
0
0
-
0
-
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