LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 312

• Manufacturer Part Number: LPC1857FET256,551
• Description: IC MCU 32BIT 1MB FLASH 256LBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1857FET256,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 243. Status Register (STATUS, address 0x4000 4048) bit description
<Document ID>
User manual
Bit
0
1
2
3
7:4
8
9
10
16:11
29:17
30
31
Symbol
FIFO_RX_WATERM
ARK
FIFO_TX_WATERM
ARK
FIFO_EMPTY
FIFO_FULL
CMDFSMSTATES
DATA_3_STATUS
DATA_BUSY
DATA_STATE_MC_
BUSY
RESPONSE_INDEX Index of previous response, including any auto-stop sent by core.
FIFO_COUNT
DMA_ACK
DMA_REQ
18.6.19 Status Register (STATUS)
Description
FIFO reached Receive watermark level; not qualified with data
FIFO reached Transmit watermark level; not qualified with data transfer.
FIFO is empty status
FIFO is full status
Command FSM states:
0 - Idle 1 - Send init sequence
2 - Tx cmd start bit
3 - Tx cmd tx bit
4 - Tx cmd index + arg
5 - Tx cmd crc7
6 - Tx cmd end bit
7 - Rx resp start bit
8 - Rx resp IRQ response
9 - Rx resp tx bit
10 - Rx resp cmd idx
11 - Rx resp data
12 - Rx resp crc7
13 - Rx resp end bit
14 - Cmd path wait NCC
15 - Wait; CMD-to-response turnaround
NOTE: The command FSM state is represented using 19 bits. The STATUS
Register(7:4) has 4 bits to represent the command FSM states. Using these 4
bits, only 16 states can be represented. Thus three states cannot be
represented in the STATUS(7:4) register. The three states that are not
represented in the STATUS Register(7:4) are:
- Bit 16 - Wait for CCS
- Bit 17 - Send CCSD
- Bit 18 - Boot Mode
Due to this, while command FSM is in Wait for CCS state or Send CCSD or
Boot Mode?, the Status register indicates status as 0 for the bit field 7:4.
Raw selected card_data[3]; checks whether card is present
0 - card not present
1 - card present
Inverted version of raw selected card_data[0]
0 - card data not busy
1 - card data busy
Data transmit or receive state-machine is busy
FIFO count - Number of filled locations in FIFO
DMA acknowledge signal state; either dw_dma_ack or ge_dma_ack,
depending on DW-DMA or Generic-DMA selection.
DMA request signal state; either dw_dma_req or ge_dma_req, depending on
DW-DMA or Generic-DMA selection.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 18: LPC18xx SD/MMC interface
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
1
1
0
0
1
0
0
0
0
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