LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 443
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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Table 367. USB Command register in device mode (USBCMD_D - address 0x4000 7140) bit description
<Document ID>
User manual
Bit
0
1
3:2
4
5
6
7
9:8
10
11
12
13
14
Symbol
RS
RST
-
-
-
-
-
-
-
-
-
SUTW
ATDTW
21.6.2.1 Device mode
Value
0
1
0
1
-
-
-
Description
Run/Stop
Writing a 0 to this bit will cause a detach event.
Writing a one to this bit will cause the device controller to enable a pull-up
on USB_DP and initiate an attach event. This control bit is not directly
connected to the pull-up enable, as the pull-up will become disabled upon
transitioning into high-speed mode. Software should use this bit to prevent
an attach event before the device controller has been properly initialized.
Controller reset.
Software uses this bit to reset the controller. This bit is set to zero by the
Host/Device Controller when the reset process is complete. Software
cannot terminate the reset process early by writing a zero to this register.
Set to 0 by hardware when the reset process is complete.
When software writes a one to this bit, the Device Controller resets its
internal pipelines, timers, counters, state machines etc. to their initial
values. Writing a one to this bit when the device is in the attached state is
not recommended, since the effect on an attached host is undefined. In
order to ensure that the device is not in an attached state before initiating a
device controller reset, all primed endpoints should be flushed and the
USBCMD Run/Stop bit should be set to 0.
Not used in device mode.
Not used in device mode.
Not used in device mode.
Not used in device mode. Writing a one to this bit when the device mode is
selected, will have undefined results.
Reserved. These bits should be set to 0.
Not used in Device mode.
Reserved.These bits should be set to 0.
Not used in Device mode.
Reserved.These bits should be set to 0.
Setup trip wire
During handling a setup packet, this bit is used as a semaphore to ensure
that the setup data payload of 8 bytes is extracted from a QH by the DCD
without being corrupted. If the setup lockout mode is off (see USBMODE
register) then there exists a hazard when new setup data arrives while the
DCD is copying the setup data payload from the QH for a previous setup
packet. This bit is set and cleared by software and will be cleared by
hardware when a hazard exists. (See
This bit is used as a semaphore to ensure the to proper addition of a new
dTD to an active (primed) endpoint’s linked list. This bit is set and cleared
by software during the process of adding a new dTD. See also
Section
This bit shall also be cleared by hardware when its state machine is hazard
region for which adding a dTD to a primed endpoint may go unrecognized.
Add dTD trip wire
20.10.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 21: LPC18xx USB1 Host/Device controller
Section
20.10).
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
0
-
-
-
0
0
0
0
Access
R/W
R/W
-
-
-
-
-
-
-
-
-
R/W
R/W
443 of 1164
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