LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 867
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
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Price
Company:
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
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10 000
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User manual
37.8.3 Slave Receiver mode
In the slave receiver mode, data bytes are received from a master transmitter. To initialize
the slave receiver mode, write any of the Slave Address registers (ADR0-3) and write the
I
Table 815. CONSET used to configure Slave mode
I2EN must be set to 1 to enable the I
its own slave address or the General Call address. The STA, STO and SI bits are set to 0.
After ADR and CONSET are initialized, the I
own address or general address followed by the data direction bit. If the direction bit is 0
(W), it enters slave receiver mode. If the direction bit is 1 (R), it enters slave transmitter
mode. After the address and direction bit have been received, the SI bit is set and a valid
status code can be read from the Status register (STAT). Refer to
codes and actions.
2
Bit
Symbol
Value
Fig 134. A Master Receiver switches to Master Transmitter after sending Repeated START
Fig 135. Format of Slave Receiver mode
C Control Set register (CONSET) as shown in
S
S
from Master to Slave
from Slave to Master
From master to slave
From slave to master
SLA
SLAVE ADDRESS
7
-
-
R
All information provided in this document is subject to legal disclaimers.
A
6
I2EN
1
Rev. 00.13 — 20 July 2011
DATA
n bytes data transmitted
RW=0
5
STA
0
A
2
DATA
A
C function. AA bit must be set to 1 to acknowledge
4
STO
0
2
A
DATA
C interface waits until it is addressed by its
Chapter 37: LPC18xx I2C-bus interface
Table
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
Sr = Repeated START condition
Sr
3
SI
0
815.
SLA
n bytes data received
A = Acknowledge (SDA low)
A = Not acknowledge (SDA high)
S = START condition
P = STOP condition
SLA = Slave Address
Sr = Repeated START condition
A
2
AA
1
W
DATA
Table 822
A
UM10430
-
1
-
© NXP B.V. 2011. All rights reserved.
DATA
A/A
for the status
867 of 1164
A
0
-
-
P/Sr
P
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