LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 291

• Manufacturer Part Number: LPC1857FET256,551
• Description: IC MCU 32BIT 1MB FLASH 256LBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1857FET256,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
16.8.5.1.1 Programming the DMA controller for scatter/gather DMA
16.8.5.1 Linked list items
16.8.5 Scatter/gather
Scatter/gather is supported through the use of linked lists. This means that the source and
destination areas do not have to occupy contiguous areas in memory. Where
scatter/gather is not required, the CLLI Register must be set to 0.
The source and destination data areas are defined by a series of linked lists. Each Linked
List Item (LLI) controls the transfer of one block of data, and then optionally loads another
LLI to continue the DMA operation, or stops the DMA stream. The first LLI is programmed
into the DMA Controller.
The data to be transferred described by a LLI (referred to as the packet of data) usually
requires one or more DMA bursts (to each of the source and destination).
A Linked List Item (LLI) consists of four words. These words are organized in the following
order:
Note: The CCONFIG DMA channel Configuration Register is not part of the linked list
item.
To program the DMA Controller for scatter/gather DMA:
1. CSRCADDR
2. CDESTADDR
3. CLLI
4. CCONTROL
1. Write the LLIs for the complete DMA transfer to memory. Each linked list item contains
2. Choose a free DMA channel with the priority required. DMA channel 0 has the highest
3. Write the first linked list item, previously written to memory, to the relevant channel in
4. Write the channel configuration information to the channel Configuration Register and
•
•
a 7-transfer burst starting at address 0x0C000024
a 9-transfer burst starting at address 0x0C000040.
four words:
– Source address.
– Destination address.
– Pointer to next LLI.
– Control word.
The last LLI has its linked list word pointer set to 0.
priority and DMA channel 7 the lowest priority.
the DMA Controller.
set the Channel Enable bit. The DMA Controller then transfers the first and then
subsequent packets of data as each linked list item is loaded.
All information provided in this document is subject to legal disclaimers.
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Rev. 00.13 — 20 July 2011
UM10430
© NXP B.V. 2011. All rights reserved.
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