LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 697
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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30.8 Block diagram
30.9 Watchdog timing examples
<Document ID>
User manual
Table 629. Watchdog Timer Window register (WINDOW - 0x4008 0018) bit description
The block diagram of the Watchdog is shown below in the
logic (PCLK - WDCLK) is not shown in the block diagram.
The following figures illustrate several aspects of Watchdog Timer operation is shown
below in
Bit
23:0
31:24
Fig 83. Watchdog block diagram
wd_clk
WDMOD
register
Symbol
WDWINDOW Watchdog window value.
-
Figure
feed sequence
All information provided in this document is subject to legal disclaimers.
84.
detect and
WDFEED
protection
WDPROTECT
(WDMOD[4])
Description
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 00.13 — 20 July 2011
feed error
÷4
Chapter 30: LPC18xx Windowed Watchdog timer (WWDT)
range
(WDMOD[2])
in
WDTOF
feed ok
WDWIND
compare
compare
underflow
0
24-bit down counter
(WDMOD[3])
WDINT
WDTC
compare
interrupt
WDTV
WDINTVAL
compare
WDRESET
(WDMOD[1])
enable count
Figure
WDCLKSEL
feed ok
(WDMOD[0])
83. The synchronization
shadow bit
WDEN
UM10430
© NXP B.V. 2011. All rights reserved.
Reset value
0xFF FFFF
NA
chip reset
watchdog
interrupt
select
697 of 1164
clock
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