LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 91

• Manufacturer Part Number: LPC1857FET256,551
• Description: IC MCU 32BIT 1MB FLASH 256LBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1857FET256,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
Fig 19. PLL0 block diagram
ENET_RX_CLK
ENET_TX_CLK
GP_CLKIN
CRYSTAL
32kHz
IDIVC
IDIVD
IDIVA
IDIVB
IDIVE
PLL1
IRC
PLL0_CTRL[27:24]
9.7.4.2 PLL0 description
CLKIN
PLL0 NPDIV[21:12]
Remark: Both PLL0 blocks are functionally identical. The PLL0 for audio applications
(PLL0 for audio) supports an additional fractional divider stage (see
The block diagram of the PLL is shown in
clkin. Pin clkout is the PLL clock output. The analog part of the PLL consists of a Phase
Frequency Detector (PFD), filter and a Current Controlled Oscillator (CCO). The PFD has
two inputs, a reference input from the (divided) external clock and one input from the
divided CCO output clock. The PFD compares the phase/frequency of these input signals
and generates a control signal if they don’t match. This control signal is fed to a filter
which drives the CCO.
The PLL contains three programmable dividers: pre-divider (N), feedback-divider (M) and
post-divider (P). The PLL contains a lock detector which measures the phase difference
between the rising edges of the input and feedback clocks. Only when this difference is
N-DIVIDER
•
•
•
•
•
•
•
•
•
Output clock range: 4.3 MHz to 550 MHz.
Programmable dividers:
– Pre-divider N (N, 1 to 2
– Feedback-divider 2 x M (M, 1 to 2
– Post-divider P x 2 (P, 1 to 2
Programmable bandwidth (integrating action, proportional action, high frequency
pole).
On-the-fly adjustment of the clock possible (dividers with handshake control).
Positive edge clocking.
Frequency limiter to avoid hang-up of the PLL.
Lock detector.
Power-down mode.
Free running mode
“1”
PLL0_CTRL[2]
Direct Input
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
PFD
Bandwidth Select P,I,R
PLL0_MDIV[31:17]
PLL0_MDIV[16:0]
M-DIVIDER
8
)
Filter
5
).
Chapter 9: LPC18xx Clock Generation Unit (CGU)
CCO
15
Figure
)
/2
PLL0_NPDIV[6:0]
P-DIVIDER
19. The clock input has to be fed to pin
PLL0_CTRL [3]
Direct Output
/2
PLL0_CTRL[4]
Section
CLKEN
PLL0_CTRL [1]
UM10430
Bypass
© NXP B.V. 2011. All rights reserved.
D
Q
9.7.5).
91 of 1164
CLKOUT