LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 338

• Manufacturer Part Number: LPC1857FET256,551
• Description: IC MCU 32BIT 1MB FLASH 256LBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1857FET256,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
Table 284. Dynamic Memory Configuration registers (DYNAMICCONFIG, address
[1]
[2]
Address mappings that are not shown in
Table 285. Address mapping
Bit
20
31:21 -
14
16 bit external bus high-performance address mapping (Row, Bank, Column)
0
0
0
0
0
0
0
0
0
0
16 bit external bus low-power SDRAM address mapping (Bank, Row, Column)
0
0
0
0
0
0
0
0
0
0
32 bit external bus high-performance address mapping (Row, Bank, Column)
1
1
1
The SDRAM column and row width and number of banks are computed automatically from the address
mapping.
The buffers must be disabled during SDRAM and SyncFlash initialization. They must also be disabled when
performing SyncFlash commands. The buffers must be enabled during normal operation.
12
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
Symbol
P
11:9 8:7
000
000
001
001
010
010
011
011
100
100
000
000
001
001
010
010
011
011
100
100
000
000
001
0x4000 5100 (DYNAMICCONFIG0), 0x4000 5120 (DYNAMICCONFIG1),
0x4000 5140 (DYNAMICCONFIG2), 0x4000 5160 (DYNAMICCONFIG3)) bit
description
All information provided in this document is subject to legal disclaimers.
00
01
00
01
00
01
00
01
00
01
00
01
00
01
00
01
00
01
00
01
00
01
00
Value Description
0
1
-
Description
16 Mb (2Mx8), 2 banks, row length = 11, column length = 9
16 Mb (1Mx16), 2 banks, row length = 11, column length = 8
64 Mb (8Mx8), 4 banks, row length = 12, column length = 9
64 Mb (4Mx16), 4 banks, row length = 12, column length = 8
128 Mb (16Mx8), 4 banks, row length = 12, column length = 10
128 Mb (8Mx16), 4 banks, row length = 12, column length = 9
256 Mb (32Mx8), 4 banks, row length = 13, column length = 10
256 Mb (16Mx16), 4 banks, row length = 13, column length = 9
512 Mb (64Mx8), 4 banks, row length = 13, column length = 11
512 Mb (32Mx16), 4 banks, row length = 13, column length = 10
16 Mb (2Mx8), 2 banks, row length = 11, column length = 9
16 Mb (1Mx16), 2 banks, row length = 11, column length = 8
64 Mb (8Mx8), 4 banks, row length = 12, column length = 9
64 Mb (4Mx16), 4 banks, row length = 12, column length = 8
128 Mb (16Mx8), 4 banks, row length = 12, column length = 10
128 Mb (8Mx16), 4 banks, row length = 12, column length = 9
256 Mb (32Mx8), 4 banks, row length = 13, column length = 10
256 Mb (16Mx16), 4 banks, row length = 13, column length = 9
512 Mb (64Mx8), 4 banks, row length = 13, column length = 11
512 Mb (32Mx16), 4 banks, row length = 13, column length = 10
16 Mb (2Mx8), 2 banks, row length = 11, column length = 9
16 Mb (1Mx16), 2 banks, row length = 11, column length = 8
64 Mb (8Mx8), 4 banks, row length = 12, column length = 9
Rev. 00.13 — 20 July 2011
Write protect.
Writes not protected (POR reset value).
Writes protected.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Chapter 19: LPC18xx External Memory Controller (EMC)
Table 285
are reserved.
UM10430
© NXP B.V. 2011. All rights reserved.
338 of 1164
Reset
value
0
-