LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 946
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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Table 888. Interrupt Clear-Enable Register 0 (ICER0 - address 0xE000 E180) bit description
<Document ID>
User manual
Bit
23
24
25
26
27
28
29
30
31:
30
Symbol
ICE_SSP1
ICE_USART0
ICE_UART1
ICE_USART2
ICE_USART3
ICE_I2S
ICE_AES
ICE_SPIFI
-
42.1.8.3 Interrupt Set-Pending Register 0 register
The ISPR0 register allows setting the pending state of the first 32 peripheral interrupts, or
for reading the pending state of those interrupts. Clearing the pending state of interrupts is
done through the ICPR0 register
Description
SSP1 interrupt disable.
Write: writing 0 has no effect, writing 1 disables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
USART0 interrupt disable.
Write: writing 0 has no effect, writing 1 disables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
UART1 interrupt disable.
Write: writing 0 has no effect, writing 1 disables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
USART2 interrupt disable.
Write: writing 0 has no effect, writing 1 disables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
USART3 interrupt disable.
Write: writing 0 has no effect, writing 1 disables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
I2S interrupt disable.
Write: writing 0 has no effect, writing 1 disables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
AES interrupt disable.
Write: writing 0 has no effect, writing 1 disables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
SPIFI interrupt disable.
Write: writing 0 has no effect, writing 1 disables the interrupt.
Read: 0 indicates that the interrupt is disabled, 1 indicates that the interrupt is enabled.
Reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
(Section
42.1.8.4).
Chapter 42: Appendix
…continued
UM10430
© NXP B.V. 2011. All rights reserved.
946 of 1164
Reset
value
0
0
0
0
0
0
0
0
0
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