LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 661
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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User manual
Dead-time counter
When the a channel’s DTE bit is set in CON, the dead-time counter delays the
passive-to-active transitions of both MCO outputs. The dead-time counter starts counting
down, from the channel’s DT value (in the DT register) to 0, whenever the channel’s A or
B output changes from active to passive. The transition of the other output from passive to
active is delayed until the dead-time counter reaches 0. During the dead time, the MCOA
and MCOB output levels are both passive.
mode with dead time, and
Fig 75. Center-aligned PWM waveform without dead time, POLA = 0
Fig 76. Edge-aligned PWM waveform with dead time, POLA = 0
MCOB
MCOA
MCOB
MCOA
All information provided in this document is subject to legal disclaimers.
0
0
active
passive
active
passive
Rev. 00.13 — 20 July 2011
Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM)
Figure 77
MAT
MAT
passive
active
DT
timer reset
passive
active
shows center-aligned operation with dead time.
LIM
LIM
passive
Figure 76
active
DT
MAT
MAT
passive
active
shows operation in edge aligned
DT
timer reset
passive
active
LIM
0
DT
LIM
UM10430
passive
active
© NXP B.V. 2011. All rights reserved.
POLA = 0
POLA = 0
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