LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 821

• Manufacturer Part Number: LPC1857FET256,551
• Description: IC MCU 32BIT 1MB FLASH 256LBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1857FET256,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
36.6.2.3 CAN message interface command mask registers
The control bits of the IFx Command Mask Register specify the transfer direction and
select which of the IFx Message Buffer Registers are source or target of the data
transfer.The functions of the register bits depend on the transfer direction (read or write)
which is selected in the WR/RD bit (bit 7) of this Command mask register.
Select the WR/RD to
Transfer direction Write
Table 764. CAN message interface command mask registers write direction (IF1_CMDMSK,
Bit
0
1
2
3
4
5
one for the Write transfer direction (write to message RAM)
zero for the Read transfer direction (read from message RAM)
Symbol
DATA_B
DATA_A
TXRQST
CLRINTPND
CTRL
ARB
address 0x400E 2024 (C_CAN0) and 0x400A 4024 (C_CAN1)) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Value Description
0
1
0
1
0
1
-
0
1
0
1
Access data bytes 4-7
Data bytes 4-7 unchanged.
Transfer data bytes 4-7 to message object.
Access data bytes 0-3
Data bytes 0-3 unchanged.
Transfer data bytes 0-3 to message object.
Access transmission request bit
No transmission request. TXRQSRT bit
unchanged in IF1/2_MCTRL.
Remark: If a transmission is requested by
programming this bit, the TXRQST bit in the
CANIFn_MCTRL register is ignored.
Request a transmission. Set the TXRQST bit
IF1/2_MCTRL.
This bit is ignored in the write direction.
Access control bits
Control bits unchanged.
Transfer control bits to message object
Access arbitration bits
Arbitration bits unchanged.
Transfer Identifier, DIR, XTD, and MSGVAL
bits to message object.
Chapter 36: LPC18xx C_CAN
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
0
0
821 of 1164
Access
R/W
R/W
R/W
R/W
R/W
R/W