LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 84
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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User manual
9.6.10 Output stage 1 control register
9.6.9 Output stage 0 control register
Table 64.
This register controls the BASE_SAFE_CLK to the watchdog oscillator. The only possible
clock source for this base clock is the IRC.
Table 65.
This register controls the BASE_USB0_CLK to the High-speed USB0. The only possible
clock source for this base clock is the PLL0 (USB) output.
Bit
27:24
31:28
Bit
0
10:1
11
23:12
28:24
31:29
Symbol
CLK_SEL
-
Symbol
PD
-
AUTOBLOCK
-
CLK_SEL
-
IDIVE control register (IDIVE_CTRL, address 0x4005 0058) bit description
Output stage 0 control register (OUTCLK_0_CTRL, address 0x4005 005C) bit
description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Value
0x00
0x01
0x02
0x03
0x04
0x06
0x08
0x09
0x0C
Value
0
1
0
1
0x01
Description
Clock-source selection. All other values are
reserved.
32 kHz oscillator
ENET_RX_CLK
ENET_TX_CLK
GP_CLKIN
Crystal oscillator
PLL0 (for audio)
PLL1
IDIVA
Reserved
Description
Output stage power down
Output stage enabled (default)
power-down
Reserved
Block clock automatically during frequency
change
Autoblocking disabled
Autoblocking enabled
Reserved
Clock source selection. All other values
are reserved.
Reserved
IRC (default)
IRC (default)
Chapter 9: LPC18xx Clock Generation Unit (CGU)
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
-
0
-
0x01
-
Reset
value
0x01
-
Access
R/W
-
R/W
-
R/W
-
Access
R/W
-
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