LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 528
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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User manual
Fig 50. Transmitter descriptor fields - enhanced format
TDES2
TDES3
TDES4
TDES5
TDES6
TDES7
TDES0
TDES1
31
W
O
N
R
E
S
is written into TDES6 and TDES7. This is indicated by the status bit TTSS: Transmit
Timestamp Status. (bit-17 of TDES0). This is shown in
and TDES7 are mentioned in
When either Advanced Timestamp or IPC Offload (Type 2) features is enabled, the SW
should set the DMA Bus Mode register[7], so that the DMA operates with extended
descriptor size. When this control bit is reset, the TDES4-TDES7 descriptor space are not
valid.
The DMA always reads or fetches four DWORDS of the descriptor from system memory
to obtain the buffer and control information as shown in
timestamp feature support is enabled, TDES0 has additional control bits[6:3] for channel 1
and channel 2. For channel 0, the bits 6:3 are ignored. The bits 6:3 are described in
Table
[30:26]
Ctrl
437.
Buffer 2 Byte Count [28:16]
Buffer 2 Address [31:0] or Next Descriptor Address [31:0]
T
T
S
E
R
E
S
All information provided in this document is subject to legal disclaimers.
[23:20]
Transmit Time Stamp High [31:0]
Transmit Time Stamp Low [31:0]
Ctrl
Rev. 00.13 — 20 July 2011
Buffer 1 Address [31:0]
R
E
S
Table 441
Reserved
Reserved
T
T
T
S
R
E
S
to
Table
Buffer 1 Byte Count [12:0]
442.
Status [16:0]
Figure
Figure
Chapter 22: LPC18xx Ethernet
50. The contents of TDES6
51. When Advanced
UM10430
© NXP B.V. 2011. All rights reserved.
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