LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 555

• Manufacturer Part Number: LPC1857FET256,551
• Description: IC MCU 32BIT 1MB FLASH 256LBGA
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1857FET256,551

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
<Document ID>
User manual
23.6.10 Masked Interrupt Status register
23.6.11 Interrupt Clear register
Table 464. Raw Interrupt Status register (INTRAW, address 0x4000 8020) bit description
The INTSTAT register is Read-Only, and contains a bit-by-bit logical AND of the INTRAW
register and the INTMASK register. A logical OR of all interrupts is provided to the system
interrupt controller.
Table 465. Masked Interrupt Status register (INTSTAT, address 0x4000 8024) bit description
The INTCLR register is Write-Only. Writing a logic 1 to the relevant bit clears the
corresponding interrupt.
Bits
3
4
31:5
Bits
0
1
2
3
4
31:5
Function
VCOMPRIS
BERRAW
-
Function
-
FUFMIS
LNBUMIS
VCOMPMIS
BERMIS
-
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Vertical compare raw interrupt status.
Set when one of the four vertical regions is reached, as selected
by the LcdVComp bits in the CTRL register.
Generates an interrupt if the VCompIM bit in the INTMSK
register is set.
AHB master bus error raw interrupt status.
Set when the AHB master interface receives a bus error
response from a slave.
Generates an interrupt if the BERIM bit in the INTMSK register is
set.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
FIFO underflow masked interrupt status.
Set when the both the FUFRIS bit in the INTRAW register and
the FUFIM bit in the INTMSK register are set.
LCD next address base update masked interrupt status.
Set when the both the LNBURIS bit in the INTRAW register and
the LNBUIM bit in the INTMSK register are set.
Vertical compare masked interrupt status.
Set when the both the VCompRIS bit in the INTRAW register
and the VCompIM bit in the INTMSK register are set.
AHB master bus error masked interrupt status.
Set when the both the BERRAW bit in the INTRAW register and
the BERIM bit in the INTMSK register are set.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Chapter 23: LPC18xx LCD
UM10430
© NXP B.V. 2011. All rights reserved.
555 of 1164
Reset
value
0x0
0x0
-
Reset
value
-
0x0
0x0
0x0
0x0
-