LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 43
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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User manual
Table 19.
Bit
4
5
6
7
8
9
10
11
12
Symbol
ATIMER_L
RTC_L
BOD_L
WWDT_L
ETH_L
USB0_L
USB1_L
-
CAN_L
Level configuration register (HILO - address 0x4004 4000) bit description
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
0
1
0
1
0
1
0
1
-
0
1
Rev. 00.13 — 20 July 2011
Level detect mode for alarm timer event.
Detect LOW level if bit 4 in the EDGE register is 0. Detect
falling edge if bit 4 in the EDGE register is 1.
Detect HIGH level if bit 4 in the EDGE register is 0. Detect
rising edge if bit 4 in the EDGE register is 1.
Level detect mode for RTC event.
Detect LOW level if bit 5 in the EDGE register is 0. Detect
falling edge if bit 5 in the EDGE register is 1.
Detect HIGH level if bit 5 in the EDGE register is 0. Detect
rising edge if bit 5 in the EDGE register is 1.
Level detect mode for BOD event.
Detect LOW level if bit 6 in the EDGE register is 0. Detect
falling edge if bit 6 in the EDGE register is 1.
Detect HIGH level if bit 6 in the EDGE register is 0. Detect
rising edge if bit 6 in the EDGE register is 1.
Level detect mode for WWDTD event.
Detect LOW level if bit 7 in the EDGE register is 0. Detect
falling edge if bit 7 in the EDGE register is 1.
Detect HIGH level if bit 7 in the EDGE register is 0. Detect
rising edge if bit 7 in the EDGE register is 1.
Detect LOW level if bit 8 in the EDGE register is 0. Detect
falling edge if bit 8 in the EDGE register is 1.
Detect HIGH level if bit 8 in the EDGE register is 0. Detect
rising edge if bit 8 in the EDGE register is 1.
Detect LOW level if bit 9 in the EDGE register is 0. Detect
falling edge if bit 9 in the EDGE register is 1.
Detect HIGH level if bit 9 in the EDGE register is 0. Detect
rising edge if bit 9 in the EDGE register is 1.
Detect LOW level if bit 10 in the EDGE register is 0. Detect
falling edge if bit 10 in the EDGE register is 1.
Detect HIGH level if bit 10 in the EDGE register is 0.
Detect rising edge if bit 10 in the EDGE register is 1.
Reserved.
Level detect mode for C_CAN event.
Detect LOW level if bit 12 in the EDGE register is 0. Detect
falling edge if bit 12 in the EDGE register is 1.
Detect HIGH level if bit 12 in the EDGE register is 0.
Detect rising edge if bit 12 in the EDGE register is 1.
Chapter 6: LPC18xx Event router
UM10430
© NXP B.V. 2011. All rights reserved.
43 of 1164
Reset
value
0
0
0
0
0
0
0
0
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