LPC1857FET256,551 NXP Semiconductors, LPC1857FET256,551 Datasheet - Page 650
LPC1857FET256,551
Manufacturer Part Number
LPC1857FET256,551
Description
IC MCU 32BIT 1MB FLASH 256LBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1857FET256,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
1MB (1M x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-LBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC1857FET256,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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User manual
26.7.9.2 MCPWM Interrupt Enable set address
Table 562. MCPWM Interrupt Enable read address (INTEN - 0x400A 0050) bit description
Writing ones to this write-only address sets the corresponding bits in INTEN, thus
enabling interrupts.
Table 563. MCPWM interrupt enable set register (INTEN_SET - address 0x400A 0054) bit
Bit
5
6
7
8
9
10
14:11
15
31:16
Bit
0
1
2
3
4
5
6
Symbol
ILIM0_SET
IMAT0_SET
ICAP0_SET
-
ILIM1_SET
IMAT1_SET
ICAP1_SET
description
Symbol
IMAT1
ICAP1
-
ILIM2
IMAT2
ICAP2
-
ABORT
-
All information provided in this document is subject to legal disclaimers.
Value
0
1
0
1
0
1
0
1
0
1
0
1
Description
Writing a one sets the corresponding bit in INTEN, thus enabling
the interrupt.
Writing a one sets the corresponding bit in INTEN, thus enabling
the interrupt.
Writing a one sets the corresponding bit in INTEN, thus enabling
the interrupt.
Reserved.
Writing a one sets the corresponding bit in INTEN, thus enabling
the interrupt.
Writing a one sets the corresponding bit in INTEN, thus enabling
the interrupt.
Writing a one sets the corresponding bit in INTEN, thus enabling
the interrupt.
Rev. 00.13 — 20 July 2011
Chapter 26: LPC18xx Motor Control PWM (MOTOCONPWM)
Description
Match interrupt for channel 1.
Interrupt disabled.
Interrupt enabled.
Capture interrupt for channel 1.
Interrupt disabled.
Interrupt enabled.
Reserved.
Limit interrupt for channel 2.
Interrupt disabled.
Interrupt enabled.
Match interrupt for channel 2.
Interrupt disabled.
Interrupt enabled.
Capture interrupt for channel 2.
Interrupt disabled.
Interrupt enabled.
Reserved.
Fast abort interrupt.
Interrupt disabled.
Interrupt enabled.
Reserved.
UM10430
© NXP B.V. 2011. All rights reserved.
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