DS21Q55 Maxim Integrated Products, DS21Q55 Datasheet - Page 105

IC TXRX QUAD T1/E1/J1 SCT 256BGA

DS21Q55

Manufacturer Part Number
DS21Q55
Description
IC TXRX QUAD T1/E1/J1 SCT 256BGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS21Q55

Function
Transceiver
Interface
E1, J1, T1
Number Of Circuits
4
Voltage - Supply
3.14 V ~ 3.47 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
256-BGA
Includes
BERT Generator and Detector, Dual HDLC Controllers
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power (watts)
-

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16.
The receive channel blocking registers (RCBR1/RCBR2/RCBR3/RCBR4) and the transmit channel
blocking registers (TCBR1/TCBR2/TCBR3/TCBR4) control RCHBLK and TCHBLK pins, respectively.
The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced either high or low
during individual channels. These outputs can be used to block clocks to a USART or LAPD controller in
ISDN-PRI applications. When the appropriate bits are set to a 1, the RCHBLK and TCHBLK pins are
held high during the entire corresponding channel time. Channels 25 through 32 are ignored when the
device is operated in the T1 mode.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Receive Channels 1 to 8 Channel Blocking Control Bits (CH1 to CH8)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 7/Receive Channels 9 to 16 Channel Blocking Control Bits (CH9 to CH16)
CHANNEL BLOCKING REGISTERS
0 = force the RCHBLK pin to remain low during this channel time
1 = force the RCHBLK pin high during this channel time
0 = force the RCHBLK pin to remain low during this channel time
1 = force the RCHBLK pin high during this channel time
CH16
CH8
7
0
7
0
CH15
CH7
RCBR1
Receive Channel Blocking Register 1
88h
RCBR2
Receive Channel Blocking Register 2
89h
6
0
6
0
CH14
CH6
5
0
5
0
CH13
CH5
4
0
4
0
105 of 237
CH12
CH4
0
0
3
3
CH11
CH3
2
0
2
0
CH10
CH2
1
0
1
0
CH1
CH9
0
0
0
0

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