DS21Q55 Maxim Integrated Products, DS21Q55 Datasheet - Page 166

• Manufacturer Part Number: DS21Q55
• Description: IC TXRX QUAD T1/E1/J1 SCT 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q55

• Function: Transceiver
• Interface: E1, J1, T1
• Number Of Circuits: 4
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Includes: BERT Generator and Detector, Dual HDLC Controllers
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -

DS21Q55 Quad T1/E1/J1 Transceiver
23.
PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND
DETECTION
The DS21Q55 has the ability to generate and detect a repeating bit pattern from one to eight bits or 16
bits in length. This function is available only in T1 mode. To transmit a pattern, the user loads the
pattern into the transmit code-definition registers (TCD1 and TCD2) and selects the proper length of the
pattern by setting the TC0 and TC1 bits in the in-band code control (IBCC) register. When generating a
1-, 2-, 4-, 8-, or 16-bit pattern, both transmit code-definition registers must be filled with the proper code.
Generation of a 3-, 5-, 6-, and 7-bit pattern only requires TCD1 to be filled. Once this is accomplished,
the pattern is transmitted as long as the TLOOP control bit (T1CCR1.0) is enabled. Normally (unless the
transmit formatter is programmed to not insert the F-bit position) the framer overwrites the repeating
pattern once every 193 bits to send the F-bit position.
For example, to transmit the standard “loop-up” code for CSUs, which is a repeating pattern of
...10000100001... , set TCD1 = 80h, IBCC = 0, and T1CCR1.0 = 1.
The framer has three programmable pattern detectors. Typically two of the detectors are used for “loop-
up” and “loop-down” code detection. The user programs the codes to be detected in the receive up-code
definition (RUPCD1 and RUPCD2) registers and the receive down-code definition (RDNCD1 and
RDNCD2) registers, and the length of each pattern is selected through the IBCC register. There is a third
detector (spare) that is defined and controlled through the RSCD1/RSCD2 and RSCC registers. When
detecting a 16-bit pattern, both receive code-definition registers are used together to form a 16-bit
register. For 8-bit patterns, both receive code-definition registers are filled with the same value. Detection
of a 1-, 2-, 3-, 4-, 5-, 6-, and 7-bit pattern only requires the first receive code-definition register to be
filled. The framer detects repeating pattern codes in both framed and unframed circumstances with bit
error rates as high as 10E-2. The detectors are capable of handling both F-bit inserted and F-bit overwrite
patterns. Writing the least significant byte of the receive code-definition register resets the integration
period for that detector. The code detector has a nominal integration period of 36ms. Hence, after about
36ms of receiving a valid code, the proper status bit (LUP at SR3.5, LDN at SR3.6, and LSPARE at
SR3.7) is set to a 1. Normally codes are sent for a period of five seconds. It is recommended that the
software poll the framer every 50ms to 1000ms until five seconds has elapsed to ensure the code is
continuously present.
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