DS21Q55 Maxim Integrated Products, DS21Q55 Datasheet - Page 57

IC TXRX QUAD T1/E1/J1 SCT 256BGA

DS21Q55

Manufacturer Part Number
DS21Q55
Description
IC TXRX QUAD T1/E1/J1 SCT 256BGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS21Q55

Function
Transceiver
Interface
E1, J1, T1
Number Of Circuits
4
Voltage - Supply
3.14 V ~ 3.47 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
256-BGA
Includes
BERT Generator and Detector, Dual HDLC Controllers
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power (watts)
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS21Q55
Manufacturer:
DS
Quantity:
959
Part Number:
DS21Q55
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS21Q552
Manufacturer:
DS
Quantity:
7
Part Number:
DS21Q552
Manufacturer:
DALLAS
Quantity:
319
Part Number:
DS21Q552
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS21Q552+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS21Q552BN+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS21Q552N+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS21Q554
Manufacturer:
DS
Quantity:
20
Part Number:
DS21Q554
Manufacturer:
AD
Quantity:
301
Part Number:
DS21Q554
Manufacturer:
DALLAS
Quantity:
20 000
Part Number:
DS21Q554B+
Manufacturer:
MAXIM/美信
Quantity:
20 000
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Frame Bit-Error Event (FBE). Set when an Ft (D4) or FPS (ESF) framing bit is received in error.
Bit 1/B8ZS Codeword Detect Event (B8ZS). Set when a B8ZS codeword is detected at RPOS and RNEG
independent of whether the B8ZS mode is selected or not by T1TCR2.7. Useful for automatically setting the line
coding.
Bit 2/Severely Errored Framing Event (SEFE). Set when two out of six framing bits (Ft or FPS) are received in
error.
Bit 3/Sixteen Zero-Detect Event (16ZD). Set when a string of at least 16 consecutive 0s (regardless of the length
of the string) have been received at RPOSI and RNEGI.
Bit 4/Eight Zero-Detect Event (8ZD). Set when a string of at least eight consecutive 0s (regardless of the length
of the string) have been received at RPOSI and RNEGI.
Bit 5/Change-of-Frame Alignment Event (COFA). Set when the last resync resulted in a change-of-frame or
multiframe alignment.
Bit 6/Transmit Pulse-Density Violation Event (TPDV). Set when the transmit data stream does not meet the
ANSI T1.403 requirements for pulse density.
Bit 7/Receive Pulse-Density Violation Event (RPDV). Set when the receive data stream does not meet the ANSI
T1.403 requirements for pulse density.
RPDV
7
0
TPDV
INFO1
Information Register 1
10h
6
0
COFA
5
0
8ZD
4
0
57 of 237
16ZD
0
3
SEFE
2
0
B8ZS
1
0
FBE
0
0

Related parts for DS21Q55