DS21Q55 Maxim Integrated Products, DS21Q55 Datasheet - Page 134
![IC TXRX QUAD T1/E1/J1 SCT 256BGA](/photos/6/82/68222/406-256-bga_sml.jpg)
DS21Q55
Manufacturer Part Number
DS21Q55
Description
IC TXRX QUAD T1/E1/J1 SCT 256BGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS21Q55.pdf
(237 pages)
Specifications of DS21Q55
Function
Transceiver
Interface
E1, J1, T1
Number Of Circuits
4
Voltage - Supply
3.14 V ~ 3.47 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
256-BGA
Includes
BERT Generator and Detector, Dual HDLC Controllers
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power (watts)
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS21Q552
Manufacturer:
DALLAS
Quantity:
319
Company:
Part Number:
DS21Q552BN+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS21Q554
Manufacturer:
DALLAS
Quantity:
20 000
Part Number:
DS21Q554B+
Manufacturer:
MAXIM/美信
Quantity:
20 000
21.2.1 FIFO Control
The FIFO control register (HxFC) controls and sets the watermarks for the transmit and receive FIFOs.
Bits 3, 4, and 5 set the transmit low watermark and the lower 3 bits set the receive high watermark.
When the transmit FIFO empties below the low watermark, the TLWM bit in the appropriate HDLC
status register SR6 or SR7 is set. TLWM is a real-time bit and remains set as long as the transmit FIFO’s
read pointer is below the watermark. If enabled, this condition can also cause an interrupt through the INT
pin.
When the receive FIFO fills above the high watermark, the RHWM bit in the appropriate HDLC status
register is set. RHWM is a real-time bit and remains set as long as the receive FIFO’s write pointer is
above the watermark. If enabled, this condition can also cause an interrupt through the INT pin.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 2/Receive FIFO High-Watermark Select (RFHWM0 to RFHWM2)
Bits 3 to 5/Transmit FIFO Low-Watermark Select (TFLWM0 to TFLWM2)
Bits 6, 7/Unused, must be set to 0 for proper operation
RFHWM2
TFLWM2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
—
7
0
RFHWM1
TFLWM1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
—
6
0
H1FC, H2FC
HDLC # 1 FIFO Control
HDLC # 2 FIFO Control
91h, A1h
RFHWM0
TFLWM0
TFLWM2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
5
0
Transmit FIFO Watermark
Receive FIFO Watermark
TFLWM1
4
0
134 of 237
(bytes)
(bytes)
112
112
16
32
48
64
80
96
16
32
48
64
80
96
4
4
TFLWM0
3
0
RFHWM2
2
0
RFHWM1
1
0
RFHWM0
0
0