DS21Q55 Maxim Integrated Products, DS21Q55 Datasheet - Page 141

• Manufacturer Part Number: DS21Q55
• Description: IC TXRX QUAD T1/E1/J1 SCT 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q55

• Function: Transceiver
• Interface: E1, J1, T1
• Number Of Circuits: 4
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Includes: BERT Generator and Detector, Dual HDLC Controllers
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 0 to 2/Receive Packet Status (PS0 to PS2). These are real-time bits indicating the status as of the last read of
the receive FIFO.
Bit 3/Receive FIFO Empty (REMPTY). A real-time bit that is set high when the receive FIFO is empty.
Bit 4/Transmit FIFO Full (TFULL). A real-time bit that is set high when the FIFO is full.
Bit 5/Transmit FIFO Empty (TEMPTY). A real-time bit that is set high when the FIFO is empty.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/HDLC #1 Opening Byte Event (H1OBT). Set when the next byte available in the receive FIFO is the first
byte of a message.
Bit 1/HDLC #1 Transmit FIFO Underrun Event (H1UDR). Set when the transmit FIFO empties out without
having seen the TMEND bit set. An abort is automatically sent. This bit is latched and is cleared when read.
Bit 2/HDLC #2 Opening Byte Event (H2OBT). Set when the next byte available in the receive FIFO is the first
byte of a message.
Bit 3/HDLC #2 Transmit FIFO Underrun Event (H2UDR). Set when the transmit FIFO empties out without
having seen the TMEND bit set. An abort is automatically sent. This bit is latched and is cleared when read
PS2
0
0
0
0
1
PS1
0
0
1
1
0
—
7
0
—
7
0
PS0
0
1
0
1
0
—
6
0
INFO5, INFO6
HDLC #1 Information Register
HDLC #2 Information Register
2Eh, 2Fh
INFO4
HDLC Event Information Register #4
2Dh
—
6
0
In Progress
Packet OK: Packet ended with correct CRC codeword
CRC Error: A closing flag was detected, preceded by a corrupt CRC
codeword
Abort: Packet ended because an abort signal was detected (seven or
more 1s in a row).
Overrun: HDLC controller terminated reception of packet because
receive FIFO is full.
TEMPTY
—
5
0
5
0
—
TFULL
4
0
4
0
141 of 237
Packet Status
H2UDR
REMPTY
0
3
3
0
H2OBT
2
0
PS2
2
0
H1UDR
1
0
PS1
1
0
H1OBT
0
0
PS0
0
0
.